Search the dblp DataBase

Publications of Author

1. Jiun-Lang Huang, Kwang-Ting Cheng
   A sigma-delta modulation based BIST scheme for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:605-612 [Conf]
   
2. Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
   On-chip Analog Response Extraction with 1-Bit ? - Modulators. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:49-0 [Conf]
   
3. Jiun-Lang Huang
   Random Jitter Testing Using Low Tap-Count Delay Lines. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:100-105 [Conf]
   
4. Jui-Jer Huang, Jiun-Lang Huang
   A Low-Cost Jitter Measurement Technique for BIST Applications. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:336-339 [Conf]
   
5. Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
   A BIST Scheme for On-Chip ADC and DAC Testing. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:216-220 [Conf]
   
6. Jui-Jer Huang, Jiun-Lang Huang
   An Infrastructure IP for On-Chip Clock Jitter Measurement. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:186-191 [Conf]
   
7. Jiun-Lang Huang, Kwang-Ting Cheng
   Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:1021-1030 [Conf]
   
8. Jiun-Lang Huang, Kwang-Ting Cheng
   Analog Fault Diagnosis for Unpowered Circuit Boards. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:640-648 [Conf]
   
9. Jiun-Lang Huang, Kwang-Ting Cheng
   An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. [Citation Graph (0, 0)][DBLP]
   VTS, 2001, pp:380-387 [Conf]
   
10. Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng
    Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:220-225 [Conf]
    
11. Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
    Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:237-246 [Conf]
    
12. Jiun-Lang Huang
    On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:387-398 [Journal]
    
13. Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu
    A Low-Cost Jitter Measurement Technique for BIST Applications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:219-228 [Journal]
    
14. 
    Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. [Citation Graph (, )][DBLP]
    
    
15. 
    An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. [Citation Graph (, )][DBLP]
    
    
16. 
    An error tolerance scheme for 3D CMOS imagers. [Citation Graph (, )][DBLP]
    
    
17. 
    A robust ADC code hit counting technique. [Citation Graph (, )][DBLP]
    
    
18. 
    On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. [Citation Graph (, )][DBLP]
    
    
19. 
    A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. [Citation Graph (, )][DBLP]