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Wu-Tung Cheng :
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Yu Huang , Wu-Tung Cheng , Greg Crowell Using fault model relaxation to diagnose real scan chain defects. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1176-1179 [Conf ] Yu Huang , Sudhakar M. Reddy , Nilanjan Mukherjee , Chien-Chung Tsai , Omer Samman , Yahya Zaidan , Yanping Zhang , Wu-Tung Cheng Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:511-516 [Conf ] Wu-Tung Cheng Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:10-0 [Conf ] Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski Compactor Independent Direct Diagnosis. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2004, pp:204-209 [Conf ] Xiaogang Du , Sudhakar M. Reddy , Joseph Rayhawk , Wu-Tung Cheng Testing Delay Faults in Embedded CAMs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:378-383 [Conf ] Yu Huang , Wu-Tung Cheng , Cheng-Ju Hsieh , Huan-Yung Tseng , Alou Huang , Yu-Ting Hung Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:44-49 [Conf ] Yu Huang , Wu-Tung Cheng , Chien-Chung Tsai , Nilanjan Mukherjee , Omer Samman , Yahya Zaidan , Sudhakar M. Reddy Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2001, pp:265-0 [Conf ] Yu Huang , Sudhakar M. Reddy , Wu-Tung Cheng Core - Clustering Based SOC Test Scheduling Optimization. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2002, pp:405-410 [Conf ] Jay Jahangiri , Nilanjan Mukherjee , Wu-Tung Cheng , Subramanian Mahadevan , Ron Press Achieving High Test Quality with Reduced Pin Count Testing. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2005, pp:312-317 [Conf ] Wei Zou , Wu-Tung Cheng , Sudhakar M. Reddy Bridge Defect Diagnosis with Physical Information. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2005, pp:248-253 [Conf ] Wu-Tung Cheng Split Circuit Model for Test Generation. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:96-101 [Conf ] Wu-Tung Cheng , Meng-Lin Yu Differential Fault Simulation - a Fast Method Using Minimal Memory. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:424-428 [Conf ] Yu Huang , Wu-Tung Cheng Using embedded infrastructure IP for SOC post-silicon verification. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:674-677 [Conf ] Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:535-540 [Conf ] Yu Huang , Wu-Tung Cheng , Cheng-Ju Hsieh , Huan-Yung Tseng , Alou Huang , Yu-Ting Hung Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1072-1077 [Conf ] Liyang Lai , Janak H. Patel , Thomas Rinderknecht , Wu-Tung Cheng Hardware Ef.cient LBISTWith Complementary Weights. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:479-484 [Conf ] Yu Huang , Wu-Tung Cheng , Chien-Chung Tsai , Nilanjan Mukherjee , Sudhakar M. Reddy Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. [Citation Graph (0, 0)][DBLP ] ISQED, 2003, pp:99-104 [Conf ] Wu-Tung Cheng Silicon Diagnosis. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:1305- [Conf ] Wu-Tung Cheng High time for high level ATPG. [Citation Graph (0, 0)][DBLP ] ITC, 1999, pp:1113- [Conf ] Wu-Tung Cheng , Janak H. Patel Multiple-Fault Detection in Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:493-499 [Conf ] Yu Huang , Wu-Tung Cheng , Sudhakar M. Reddy , Cheng-Ju Hsieh , Yu-Ting Hung Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:319-328 [Conf ] Yu Huang , Sudhakar M. Reddy , Wu-Tung Cheng , Paul Reuter , Nilanjan Mukherjee , Chien-Chung Tsai , Omer Samman , Yahya Zaidan Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. [Citation Graph (0, 0)][DBLP ] ITC, 2002, pp:74-82 [Conf ] Yu Huang , Chien-Chung Tsai , Neelanjan Mukherjee , Omer Samman , Dan Devries , Wu-Tung Cheng , Sudhakar M. Reddy On RTL scan design. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:728-737 [Conf ] Liyang Lai , Janak H. Patel , Thomas Rinderknecht , Wu-Tung Cheng Logic BIST with Scan Chain Segmentation. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:57-66 [Conf ] Bejoy G. Oomman , Wu-Tung Cheng , John A. Waicukauski A Universal Technique for Accelerating Simulation of Scan Test Patterns. [Citation Graph (0, 0)][DBLP ] ITC, 1996, pp:135-141 [Conf ] Theo J. Powell , Wu-Tung Cheng , Joseph Rayhawk , Omer Samman , Paul Policke , Sherry Lai BIST for Deep Submicron ASIC Memories with High Performance Application. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:386-392 [Conf ] Xiaogang Du , Sudhakar M. Reddy , Wu-Tung Cheng , Joseph Rayhawk , Nilanjan Mukherjee At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:895-900 [Conf ] Yu Huang , Nilanjan Mukherjee , Chien-Chung Tsai , Omer Samman , Yahya Zaidan , Yanping Zhang , Wu-Tung Cheng , Sudhakar M. Reddy Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:511-516 [Conf ] Wei Zou , Wu-Tung Cheng , Sudhakar M. Reddy , Huaxing Tang On Methods to Improve Location Based Logic Diagnosis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:181-187 [Conf ] Xiaogang Du , Sudhakar M. Reddy , Don E. Ross , Wu-Tung Cheng , Joseph Rayhawk Memory BIST Using ESP. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:243-248 [Conf ] Liyang Lai , Thomas Rinderknecht , Wu-Tung Cheng , Janak H. Patel Logic BIST Using Constrained Scan Cells. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:199-205 [Conf ] Xijiang Lin , Wu-Tung Cheng , Irith Pomeranz , Sudhakar M. Reddy SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:205-212 [Conf ] Wei Zou , Wu-Tung Cheng , Sudhakar M. Reddy , Huaxing Tang Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:225-230 [Conf ] Wu-Tung Cheng , Tapan J. Chakraborty Gentest: An Automatic Test-Generation System for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1989, v:22, n:4, pp:43-49 [Journal ] Wu-Tung Cheng , Janak H. Patel A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1987, v:36, n:7, pp:891-895 [Journal ] Wu-Tung Cheng , James L. Lewandowski , Eleanor Wu Optimal diagnostic methods for wiring interconnects. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1161-1166 [Journal ] Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel PROOFS: a fast, memory-efficient sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:198-207 [Journal ] At-Speed Scan Test Method for the Timing Optimization and Calibration. [Citation Graph (, )][DBLP ] Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. [Citation Graph (, )][DBLP ] On Improving Diagnostic Test Generation for Scan Chain Failures. [Citation Graph (, )][DBLP ] Improving compressed test pattern generation for multiple scan chain failure diagnosis. [Citation Graph (, )][DBLP ] PROOFS: a super fast fault simulator for sequential circuits. [Citation Graph (, )][DBLP ] Automatic Test Pattern Generation for Interconnect Open Defects. [Citation Graph (, )][DBLP ] Reducing Scan Shift Power at RTL. [Citation Graph (, )][DBLP ] Full-circuit SPICE simulation based validation of dynamic delay estimation. [Citation Graph (, )][DBLP ] Scan based speed-path debug for a microprocessor. [Citation Graph (, )][DBLP ] Speed-Path Debug Using At-Speed Scan Test Patterns. [Citation Graph (, )][DBLP ] X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP ] Survey of Scan Chain Diagnosis. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.154secs