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Shih-Hsu Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
    Fast multi-domain clock skew scheduling for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:254-259 [Conf]
  2. Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang
    Synthesis of false loop free circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
    Register binding for clock period minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:439-444 [Conf]
  4. Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
    Race-condition-aware clock skew scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:475-478 [Conf]
  5. Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
    Minimizing peak current via opposite-phase clock tree. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:182-185 [Conf]
  6. Shih-Hsu Huang, Jian-Yuan Lai
    A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    FUZZ-IEEE, 2001, pp:1054-1057 [Conf]
  7. Shih-Hsu Huang, Yow-Tyng Nieh
    Clock Period Minimization of Non-Zero Clock Skew Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:809-812 [Conf]
  8. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
    State re-encoding for peak current minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:33-38 [Conf]
  9. Shih-Hsu Huang, Chun-Hua Cheng
    A formal approach to the slack driven scheduling problem in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5633-5636 [Conf]
  10. Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
    Floorplanning with clock tree estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6244-6247 [Conf]
  11. Shih-Hsu Huang, Chu-Liao Wang
    An effective floorplan-based power distribution network design methodology under reliability constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:353-356 [Conf]
  12. Mely Chen Chi, Shih-Hsu Huang
    A Reliable Clock Tree Design Methodology for ASIC Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:269-274 [Conf]
  13. Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
    An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
  14. Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai
    High-Speed Fuzzy Inference Processor Using Active Rules Identification. [Citation Graph (0, 0)][DBLP]
    JCIS, 2006, pp:- [Conf]
  15. Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
    A new approach to schedule operations across nested-ifs and nested-loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:268-271 [Conf]
  16. Shih-Hsu Huang
    An effective low power design methodology based on interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:189-194 [Conf]
  17. Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng
    Three-dimension scheduling under multi-cycle interconnect communications. [Citation Graph (0, 0)][DBLP]
    IEICE Electronic Express, 2005, v:2, n:4, pp:108-114 [Journal]
  18. Shih-Hsu Huang, Jian-Yuan Lai
    High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2005, v:21, n:3, pp:607-626 [Journal]
  19. Shih-Hsu Huang, Yow-Tyng Nieh
    Synthesis of nonzero clock skew circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:961-976 [Journal]
  20. Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
    Clock Period Minimization with Minimum Delay Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:970-975 [Conf]
  21. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
    A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:6, pp:1681-1705 [Journal]
  22. Shih-Hsu Huang, Yow-Tyng Nieh
    Clock skew scheduling with race conditions considered. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  23. Timing driven power gating in high-level synthesis. [Citation Graph (, )][DBLP]


  24. Type-matching clock tree for zero skew clock gating. [Citation Graph (, )][DBLP]


  25. A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. [Citation Graph (, )][DBLP]


  26. Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. [Citation Graph (, )][DBLP]


  27. VLSI implementation of type-2 fuzzy inference processor. [Citation Graph (, )][DBLP]


  28. Operation Scheduling for False Loop Free Circuits. [Citation Graph (, )][DBLP]


  29. Peak Power Minimization through Power Management Scheduling. [Citation Graph (, )][DBLP]


  30. A timing driven approach for crosstalk minimization in gridded channel routing. [Citation Graph (, )][DBLP]


  31. Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. [Citation Graph (, )][DBLP]


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