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Publications of Author

1. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
   Fast multi-domain clock skew scheduling for peak current reduction. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:254-259 [Conf]
   
2. Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
   Register binding for clock period minimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:439-444 [Conf]
   
3. Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
   Race-condition-aware clock skew scheduling. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:475-478 [Conf]
   
4. Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
   Minimizing peak current via opposite-phase clock tree. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:182-185 [Conf]
   
5. Shih-Hsu Huang, Yow-Tyng Nieh
   Clock Period Minimization of Non-Zero Clock Skew Circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:809-812 [Conf]
   
6. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
   State re-encoding for peak current minimization. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:33-38 [Conf]
   
7. Shih-Hsu Huang, Yow-Tyng Nieh
   Synthesis of nonzero clock skew circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:961-976 [Journal]
   
8. Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
   Clock Period Minimization with Minimum Delay Insertion. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:970-975 [Conf]
   
9. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
   A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2007, v:23, n:6, pp:1681-1705 [Journal]
   
10. Shih-Hsu Huang, Yow-Tyng Nieh
    Clock skew scheduling with race conditions considered. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]