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Qiang Zhou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
    Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:99-102 [Conf]
  2. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:582-587 [Conf]
  3. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:588-593 [Conf]
  4. Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Analysis of buffered hybrid structured clock networks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:93-98 [Conf]
  5. Qiang Zhou, Zushun Chen
    Building a Situation-Based Language Knowledge Base. [Citation Graph (0, 0)][DBLP]
    CICLing, 2005, pp:333-336 [Conf]
  6. Qiang Zhou
    Local context templates for Chinese constituent boundary prediction. [Citation Graph (0, 0)][DBLP]
    COLING, 2000, pp:975-981 [Conf]
  7. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:176-181 [Conf]
  8. Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai
    A new algorithm for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:221-224 [Conf]
  9. Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
    Improved multilevel routing with redundant via placement for yield and reliability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:143-146 [Conf]
  10. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
    New timing and routability driven placement algorithms for FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:570-575 [Conf]
  11. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
    A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:344-349 [Conf]
  12. Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou
    Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. [Citation Graph (0, 0)][DBLP]
    ICCSA (4), 2005, pp:896-905 [Conf]
  13. Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
    A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:275-286 [Conf]
  14. Limin Ma, Qiang Zhou, Mehmet Celenk, David M. Chelberg
    Facial event mining using coupled hidden markov models. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:1405-1408 [Conf]
  15. Qiang Zhou, Limin Ma, Mehmet Celenk, David M. Chelberg
    Natural scene synthesis using multiple eigenspaces. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2003, pp:121-124 [Conf]
  16. Limin Ma, Qiang Zhou, David M. Chelberg, Mehmet Celenk
    Shape-based image retrieval with relevance feedback. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:779-782 [Conf]
  17. Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong
    A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. [Citation Graph (0, 0)][DBLP]
    ICNC (3), 2005, pp:181-184 [Conf]
  18. David M. Chelberg, Lonnie R. Welch, Cynthia R. Marling, Carl Bruggeman, Douglas Lawrence, David W. Matolak, Robert L. Williams II, Jae Y. Lew, Arvind Lakshmikumar, Matthew Gillen, Qiang Zhou, Barbara Pfarr
    A Dynamic, Real-Time Testbed for Resource Management Technology. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:88- [Conf]
  19. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    Integrated routing resource assignment for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1871-1874 [Conf]
  20. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
  21. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Layer assignment algorithm for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:85-88 [Conf]
  22. Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
    Algorithm for yield driven correction of layout. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:241-245 [Conf]
  23. Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
    Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:81-84 [Conf]
  24. Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
    Crosstalk driven routing resource assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:89-92 [Conf]
  25. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
    Shielding area optimization under the solution of interconnect crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:297-300 [Conf]
  26. Qiang Zhou, Zhihua Xiong, Jie Zhang, Yongmao Xu
    Hierarchical Neural Network Based Product Quality Prediction of Industrial Ethylene Pyrolysis Process. [Citation Graph (0, 0)][DBLP]
    ISNN (2), 2006, pp:1132-1137 [Conf]
  27. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
    Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:178-185 [Conf]
  28. Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
    Power Delivery Aware Floorplanning for Voltage Island Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:350-355 [Conf]
  29. Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
    Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:279-284 [Conf]
  30. Elliott Franco Drábek, Qiang Zhou
    Use of a Lexical Feature Database for Partial Parsing of Chinese. [Citation Graph (0, 0)][DBLP]
    NLPRS, 2001, pp:663-668 [Conf]
  31. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:257-266 [Conf]
  32. Mehmet Celenk, Qiang Zhou, David M. Chelberg
    Equal Intensity Map Texture Modeling for Natural Scene Segmentation. [Citation Graph (0, 0)][DBLP]
    SSIAI, 2002, pp:219-223 [Conf]
  33. Qiang Zhou
    Build a Large-Scale Syntactically Annotated Chinese Corpus. [Citation Graph (0, 0)][DBLP]
    TSD, 2003, pp:106-113 [Conf]
  34. Mingyu Lu, Qiang Zhou, Li Fan, Yuchang Lu, Lizhu Zhou
    Recommendation of Web Pages Based on Concept Association. [Citation Graph (0, 0)][DBLP]
    WECWIS, 2002, pp:221-227 [Conf]
  35. Qiang Zhou, Limin Ma, David M. Chelberg
    Adaptive object detection and recognition based on a feedback strategy. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 2006, v:24, n:1, pp:80-93 [Journal]
  36. Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong
    Shielding Area Optimization Under the Solution of Interconnect Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:6, pp:901-906 [Journal]
  37. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
    Crosstalk-Aware Routing Resource Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:231-236 [Journal]
  38. Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong
    Priority-Based Routing Resource Assignment Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:913-921 [Journal]
  39. Qiang Zhou, Limin Ma, Mehmet Celenk, David M. Chelberg
    Content-Based Image Retrieval Based on ROI Detection and Relevance Feedback. [Citation Graph (0, 0)][DBLP]
    Multimedia Tools Appl., 2005, v:27, n:2, pp:251-281 [Journal]
  40. Qiang Zhou, Limin Ma, David M. Chelberg, Jingbing Xue, Ellengene Peterson, Michael Rowe
    A novel machine vision application for analysis and visualization of confocal microscopic images. [Citation Graph (0, 0)][DBLP]
    Mach. Vis. Appl., 2005, v:16, n:2, pp:96-104 [Journal]
  41. Qiang Zhou, David Parrott, Matthew Gillen, David M. Chelberg, Lonnie R. Welch
    Agent-based computer vision in a dynamic, real-time environment. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2004, v:37, n:4, pp:691-705 [Journal]
  42. Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
    Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:325-345 [Journal]
  43. Qiang Zhou, Limin Ma, Mehmet Celenk, David M. Chelberg
    Object Detection and Recognition via Deformable Illumination and Deformable Shape. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:2737-2740 [Conf]
  44. Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
    Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2040-2043 [Conf]
  45. Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou
    Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3411-3414 [Conf]
  46. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong
    A novel low-power physical design methodology for MTCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  47. Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
    A novel technique integrating buffer insertion into timing driven placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  48. Huafeng Wu, Han Peng, Qiang Zhou, Min Yang, Bing Sun, Bo Yu
    P2P Multimedia Sharing over MANET. [Citation Graph (0, 0)][DBLP]
    MMM (2), 2007, pp:635-642 [Conf]
  49. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
    An efficient quadratic placement based on search space traversing technology. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:253-260 [Journal]
  50. Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
    A Yield-Driven Gridless Router. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:653-660 [Journal]

  51. Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. [Citation Graph (, )][DBLP]


  52. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. [Citation Graph (, )][DBLP]


  53. Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. [Citation Graph (, )][DBLP]


  54. Logic and Layout Aware Voltage Island Generation for Low Power Design. [Citation Graph (, )][DBLP]


  55. Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP]


  56. Information hiding for trusted system design. [Citation Graph (, )][DBLP]


  57. Behavioral level dual-vth design for reduced leakage power with thermal awareness. [Citation Graph (, )][DBLP]


  58. SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. [Citation Graph (, )][DBLP]


  59. Improve clock gating through power-optimal enable function selection. [Citation Graph (, )][DBLP]


  60. Fast congestion-aware timing-driven placement for island FPGA. [Citation Graph (, )][DBLP]


  61. MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. [Citation Graph (, )][DBLP]


  62. A hybrid optimization algorithm for the job-shop scheduling problem. [Citation Graph (, )][DBLP]


  63. A novel performance driven power gating based on distributed sleep transistor network. [Citation Graph (, )][DBLP]


  64. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  65. Decoupling capacitance efficient placement for reducing transient power supply noise. [Citation Graph (, )][DBLP]


  66. Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. [Citation Graph (, )][DBLP]


  67. DFM Based Detailed Routing Algorithm for ECP and CMP. [Citation Graph (, )][DBLP]


  68. Cell shifting aware of wirelength and overlap. [Citation Graph (, )][DBLP]


  69. Useful clock skew optimization under a multi-corner multi-mode design framework. [Citation Graph (, )][DBLP]


  70. A low power clock network placement framework. [Citation Graph (, )][DBLP]


  71. Video Coding With Key Frames Guided Super-Resolution. [Citation Graph (, )][DBLP]


  72. Throughput Performance of Marine STDMA Ad-hoc Network. [Citation Graph (, )][DBLP]


  73. Human identification using correlation metrics of iris images. [Citation Graph (, )][DBLP]


  74. Content-based video indexing and retrieval using the Radon transform and pattern matching. [Citation Graph (, )][DBLP]


  75. A Computational Framework to Integrate Different Semantic Resources. [Citation Graph (, )][DBLP]


  76. Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. [Citation Graph (, )][DBLP]


  77. Research of Time-frequency Analysis Method of Nonstationary Periodic Signal. [Citation Graph (, )][DBLP]


  78. Predicting the product yield profile and cracking degrees in an industrial ethylene pyrolysis furnace. [Citation Graph (, )][DBLP]


  79. A New Approach of Extended Chirp Scaling Algorithm for High Squint Missile-Borne SAR Data Processing. [Citation Graph (, )][DBLP]


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