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Publications of Author

1. Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
   Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:99-102 [Conf]
   
2. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
   Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:588-593 [Conf]
   
3. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
   Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:176-181 [Conf]
   
4. Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai
   Combining clustering and partitioning in quadratic placement. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2003, pp:720-723 [Conf]
   
5. Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
   Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:81-84 [Conf]
   
6. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
   An efficient quadratic placement based on search space traversing technology. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:3, pp:253-260 [Journal]
   
7. 
   An innovative Steiner tree based approach for polygon partitioning. [Citation Graph (, )][DBLP]
   
   
8. 
   Useful clock skew optimization under a multi-corner multi-mode design framework. [Citation Graph (, )][DBLP]
   
   
9. 
   A low power clock network placement framework. [Citation Graph (, )][DBLP]