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Chih-Tsun Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
    A programmable built-in self-test core for embedded memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:11-12 [Conf]
  2. Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
    A configurable AES processor for enhanced security. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:361-366 [Conf]
  3. Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Design and test of a scalable security processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:372-375 [Conf]
  4. Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
    An HMAC processor with integrated SHA-1 and MD5 algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:456-458 [Conf]
  5. Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:91-96 [Conf]
  6. Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:411-0 [Conf]
  7. Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
    On Test and Diagnostics of Flash Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:260-265 [Conf]
  8. Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:356-0 [Conf]
  9. Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
    A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:103-0 [Conf]
  10. Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
    A network security processor design based on an integrated SOC design and test platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:490-495 [Conf]
  11. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:301-306 [Conf]
  12. Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
    Optimization of regular expression pattern matching circuits on FPGA. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:12-17 [Conf]
  13. Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    Flash Memory Built-In Self-Test Using March-Like Algorithm. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:137-141 [Conf]
  14. Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
    BRAINS: A BIST Compiler for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:299-0 [Conf]
  15. Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
    Failure Factor Based Yield Enhancement for SRAM Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:20-28 [Conf]
  16. Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
    An Application-Independent Delay Testing Methodology for Island-Style FPGA. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:478-486 [Conf]
  17. Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES: A Fast Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:165-173 [Conf]
  18. Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    FAME: A Fault-Pattern Based Memory Failure Analysis Framework. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:595-598 [Conf]
  19. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
    Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:468-471 [Conf]
  20. Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
    An SOC Test Integration Platform and Its Industrial Realization. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1213-1222 [Conf]
  21. Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Diagonal Test and Diagnostic Schemes for Flash Memorie. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:37-46 [Conf]
  22. Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    March-based RAM diagnosis algorithms for stuck-at and coupling faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:758-767 [Conf]
  23. Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
    Fault Pattern Oriented Defect Diagnosis for Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:29-38 [Conf]
  24. Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:281-288 [Conf]
  25. Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Test and Diagnosis of Word-Oriented Multiport Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:248-253 [Conf]
  26. Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
    A BIST Scheme for FPGA Interconnect Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:201-206 [Conf]
  27. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation for Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:291-296 [Conf]
  28. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
    A Programmable BIST Core for Embedded DRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:59-70 [Journal]
  29. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Fault simulation and test algorithm generation for random accessmemories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:480-490 [Journal]
  30. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
    Built-in redundancy analysis for memory yield improvement. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:386-399 [Journal]

  31. A High-Throughput Low-Power AES Cipher for Network Applications. [Citation Graph (, )][DBLP]


  32. An embedded infrastructure of debug and trace interface for the DSP platform. [Citation Graph (, )][DBLP]


  33. High-speed C-testable systolic array design for Galois-field inversion. [Citation Graph (, )][DBLP]


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