The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Rei-Fu Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
    SRAM delay fault modeling and test algorithm development. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:104-109 [Conf]
  2. Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
    Defect Oriented Fault Analysis for SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:256-261 [Conf]
  3. Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang
    Fail Pattern Identification for Memory Built-In Self-Repair. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:366-371 [Conf]
  4. Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
    On Test and Diagnostics of Flash Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:260-265 [Conf]
  5. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
    A Processor-Based Built-In Self-Repair Design for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:366-371 [Conf]
  6. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:262-0 [Conf]
  7. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
    A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:393-402 [Conf]
  8. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
    MRAM Defect Analysis and Fault Modeli. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:124-133 [Conf]
  9. Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
    A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:65-69 [Conf]
  10. Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
    A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:53-0 [Conf]
  11. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:68-0 [Conf]
  12. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
    A built-in self-repair design for RAMs with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:742-745 [Journal]

  13. Fault models for embedded-DRAM macros. [Citation Graph (, )][DBLP]


  14. Economic Aspects of Memory Built-in Self-Repair. [Citation Graph (, )][DBLP]


  15. Raisin: Redundancy Analysis Algorithm Simulation. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002