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Yu-Chin Hsu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang
    Synthesis of false loop free circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho
    Zero Skew Clock Net Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:518-523 [Conf]
  3. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: A Cell Layout Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:474-479 [Conf]
  4. Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
    Advanced techniques for RTL debugging. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:362-367 [Conf]
  5. Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
    Visibility enhancement for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:13-18 [Conf]
  6. Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
    Data Path Allocation Based on Bipartite Weighted Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:499-504 [Conf]
  7. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    Optimum and Heuristic Data Path Scheduling Under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:65-70 [Conf]
  8. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    Scheduling for Functional Pipelining and Loop Winding. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:764-769 [Conf]
  9. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:481-486 [Conf]
  10. Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
    Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:585-590 [Conf]
  11. Enoch Hwang, Frank Vahid, Yu-Chin Hsu
    FSMD Functional Partitioning for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:22-27 [Conf]
  12. How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
    Cell Height Driven Transistor Sizing in a Cell Based Module Design. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:425-429 [Conf]
  13. Ting-Hai Chao, Yu-Chin Hsu
    Rectilinear Steiner Tree Construction by Local and Global Refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:432-435 [Conf]
  14. Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee
    High throughput pipelined data path synthesis by conserving the regularity of nested loops. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:450-453 [Conf]
  15. Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu
    Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:38-41 [Conf]
  16. Fur-Shing Tsai, Yu-Chin Hsu
    Data Path Construction and Refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:308-311 [Conf]
  17. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Post-routing timing optimization with routing characterization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:30-35 [Conf]
  18. Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
    Eliminating False Loops Caused by Sharing in Control Path. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:39-44 [Conf]
  19. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    A Comparison of Functional and Structural Partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:121-126 [Conf]
  20. Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
    A new approach to schedule operations across nested-ifs and nested-loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:268-271 [Conf]
  21. Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Tayung Liu, Yu-Chin Hsu
    Diagnosing Silicon Failures Based on Functional Test Patterns. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:94-98 [Conf]
  22. Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
    Combining Logic Minimization and Folding for PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:706-713 [Journal]
  23. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Timing optimization on routed designs with incremental placementand routing characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:188-196 [Journal]
  24. Ting-Hai Chao, Yu-Chin Hsu
    Rectilinear Steiner tree construction by local and global refinement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:303-309 [Journal]
  25. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: a CMOS cell compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:994-1005 [Journal]
  26. Cheng-Tsung Hwang, Yu-Chin Hsu
    Zone scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:926-934 [Journal]
  27. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    PLS: a scheduler for pipeline synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1279-1286 [Journal]
  28. Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
    A fast transistor-chaining algorithm for CMOS cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:781-786 [Journal]
  29. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:410-424 [Journal]
  30. Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu
    A formal approach to the scheduling problem in high level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:464-475 [Journal]
  31. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    SILK: a simulated evolution router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1108-1114 [Journal]
  32. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    Hybrid routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:151-157 [Journal]
  33. Fur-Shing Tsai, Yu-Chin Hsu
    STAR: An automatic data path allocator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1053-1064 [Journal]
  34. Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:217-230 [Journal]
  35. Alan Su 0002, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
    Eliminating false loops caused by sharing in control path. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:487-495 [Journal]
  36. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:181-208 [Journal]
  37. Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King
    MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:21-32 [Journal]

  38. A General Failure Candidate Ranking Framework for Silicon Debug. [Citation Graph (, )][DBLP]


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