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Publications of Author

1. Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
   A new method for constructing IP level power model based on power sensitivity. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:135-140 [Conf]
   
2. Wen-Zen Shen, Jing-Yuan Lin, Fong-Wen Wang
   Transistor reordering rules for power reduction in CMOS gates. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
   Fanout fault analysis for digital logic circuits. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:33-39 [Conf]
   
4. Wen-Jun Hsu, Wen-Zen Shen
   Coalgebraic Division for Multilevel Logic Synthesis. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:438-442 [Conf]
   
5. Tyh-Song Hwang, Chung-Len Lee, Wen-Zen Shen, Ching Ping Wu
   A Parallel Pattern Mixed-Level Fault Simulator. [Citation Graph (0, 0)][DBLP]
   DAC, 1990, pp:716-719 [Conf]
   
6. Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao
   Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:65-69 [Conf]
   
7. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
   Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:359-363 [Conf]
   
8. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
   An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1996, pp:13-17 [Conf]
   
9. Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
   A cell-based power estimation in CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:304-309 [Conf]
   
10. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A power modeling and characterization method for the CMOS standard cell library. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:400-404 [Conf]
    
11. Jing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A power modeling and characterization method for macrocells using structure information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:502-506 [Conf]
    
12. Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung
    On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:171-174 [Conf]
    
13. Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen
    A pattern compaction technique for power estimation based on power sensitivity information. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:467-470 [Conf]
    
14. Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
    Grouped input power sensitive transition an input sequence compaction technique for power estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:471-474 [Conf]
    
15. Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan
    Design of Pseudoexhaustive Testable PLA with Low Overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:887-891 [Journal]
    
16. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
    Single-fault fault-collapsing analysis in sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1559-1568 [Journal]
    
17. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
    On circuit clustering for area/delay tradeoff under capacity and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:634-642 [Journal]
    
18. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
    A structure-oriented power modeling technique for macrocells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:380-391 [Journal]
    
19. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
    ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:392-400 [Journal]