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Nilanjan Mukherjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:511-516 [Conf]
  2. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
    Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:265-0 [Conf]
  3. Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press
    Achieving High Test Quality with Reduced Pin Count Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:312-317 [Conf]
  4. Nilanjan Mukherjee
    Improving Test Quality Using Test Data Compression. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:463- [Conf]
  5. Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Software Accelerated Functional Fault Simulation for Data-Path Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:333-338 [Conf]
  6. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    On testable multipliers for fixed-width data path architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:541-547 [Conf]
  7. Nilanjan Mukherjee
    A Hybrid, Variational 3D Smoother For Orphaned Shell Meshes. [Citation Graph (0, 0)][DBLP]
    IMR, 2002, pp:379-390 [Conf]
  8. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
    Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:99-104 [Conf]
  9. Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
    Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:74-82 [Conf]
  10. Ramesh Karri, Nilanjan Mukherjee
    Versatile BIST: an integrated approach to on-line/off-line BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:910-917 [Conf]
  11. Nilanjan Mukherjee
    Cost of Test - Taking Control. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1431- [Conf]
  12. Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
    A BIST scheme for the detection of path-delay faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:422-0 [Conf]
  13. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Parameterizable Testing Scheme for FIR Filters. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:694-703 [Conf]
  14. Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
    Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1211-1220 [Conf]
  15. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:301-310 [Conf]
  16. Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee
    At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:895-900 [Conf]
  17. Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:511-516 [Conf]
  18. Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
    Embedded Test for Low Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:21-23 [Conf]
  19. Thomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji
    An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:192-197 [Conf]
  20. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Planar High Performance Ring Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:193-198 [Conf]
  21. Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self test for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:132-139 [Conf]
  22. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:58-66 [Journal]
  23. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    High Performance Dense Ring Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:83-87 [Journal]
  24. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Testing Schemes for FIR Filter Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:7, pp:674-688 [Journal]
  25. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Design of Testable Multipliers for Fixed-Width Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:7, pp:795-810 [Journal]
  26. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
    Embedded deterministic test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:776-792 [Journal]

  27. Targeting "Zero DPPM" - Can we ever get there? [Citation Graph (, )][DBLP]


  28. High Quality Bi-Linear Transfinite Meshing with Interior Point Constraints. [Citation Graph (, )][DBLP]


  29. A Mesh Morphing Technique For Geometrically Dissimilar Tessellated Surfaces. [Citation Graph (, )][DBLP]


  30. High-Speed On-Chip Event Counters for Embedded Systems. [Citation Graph (, )][DBLP]


  31. Defect Aware to Power Conscious Tests - The New DFT Landscape. [Citation Graph (, )][DBLP]


  32. X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]


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