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Chien-Chung Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:511-516 [Conf]
  2. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
    Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:265-0 [Conf]
  3. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Boolean Matching Using Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:339-344 [Conf]
  4. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Multilevel Logic Synthesis for Arithmetic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:242-247 [Conf]
  5. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Logic Synthesis for Testability. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:118-121 [Conf]
  6. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:287-290 [Conf]
  7. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
    Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:99-104 [Conf]
  8. Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
    A novel combinational testability analysis by considering signal correlation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:658-667 [Conf]
  9. Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
    Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:74-82 [Conf]
  10. Yu Huang, Chien-Chung Tsai, Neelanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
    On RTL scan design. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:728-737 [Conf]
  11. Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:511-516 [Conf]
  12. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Generalized Reed-Muller Forms as a Tool to Detect Symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:33-40 [Journal]
  13. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:2, pp:173-186 [Journal]

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