The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yahya Zaidan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:511-516 [Conf]
  2. Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
    Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:265-0 [Conf]
  3. Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
    Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:74-82 [Conf]
  4. Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:511-516 [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002