The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Chanseok Hwang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chanseok Hwang, Massoud Pedram
    Interconnect design methods for memory design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:438-443 [Conf]
  2. Chanseok Hwang, Massoud Pedram
    PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:428-431 [Conf]
  3. Chanseok Hwang, Massoud Pedram
    Timing-driven placement based on monotone cell ordering constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:201-206 [Conf]
  4. Chanseok Hwang, Peng Rong, Massoud Pedram
    Sleep transistor distribution in row-based MTCMOS designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:235-240 [Conf]
  5. Chanseok Hwang, Chang Woo Kang, Massoud Pedram
    Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:741-746 [Conf]

Search in 0.015secs, Finished in 0.015secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002