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Munehiro Matsuura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno
    Realization of Regular Ternary Logic Functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:331-0 [Conf]
  2. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno
    A hardware simulation engine based on decision diagrams (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:73-76 [Conf]
  3. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
    A fast logic simulator using a look up table cascade emulator. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:466-472 [Conf]
  4. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    On Decomposition of Kleene TDDs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:234-0 [Conf]
  5. Tsutomu Sasao, Munehiro Matsuura
    A method to decompose multiple-output logic functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:428-433 [Conf]
  6. Tsutomu Sasao, Munehiro Matsuura
    BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:373-378 [Conf]
  7. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    Realization of Multiple-Output Functions by Reconfigurable Cascades. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:388-393 [Conf]
  8. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    Implementation of Multiple-Output Functions Using PQMDDs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:199-205 [Conf]
  9. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:302-308 [Conf]
  10. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    On Designs of Radix Converters Using Arithmetic Decompositions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:3- [Conf]
  11. Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
    Representations of Logic Functions Using QRMDDs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:261-0 [Conf]
  12. Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
    Comparison of Decision Diagrams for Multiple-Output Logic Functions. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:379-384 [Conf]
  13. Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
    Average Path Length of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:9, pp:1041-1053 [Journal]
  14. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
    A CAM Emulator Using Look-Up Table Cascades. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]

  15. An Implementation of an Address Generator Using Hash Memories. [Citation Graph (, )][DBLP]


  16. Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. [Citation Graph (, )][DBLP]


  17. The Parallel Sieve Method for a Virus Scanning Engine. [Citation Graph (, )][DBLP]


  18. A virus scanning engine using a parallel finite-input memory machine and MPUs. [Citation Graph (, )][DBLP]


  19. On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. [Citation Graph (, )][DBLP]


  20. A Quaternary Decision Diagram Machine and the Optimization of its Code. [Citation Graph (, )][DBLP]


  21. A Comparison of Architectures for Various Decision Diagram Machines. [Citation Graph (, )][DBLP]


  22. A Parallel Branching Program Machine for Emulation of Sequential Circuits. [Citation Graph (, )][DBLP]


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