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Junpei Inoue: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
    Evaluation of on-chip transmission line interconnect using wire length distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:133-138 [Conf]
  2. Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
    ULSI Interconnect Length Distribution Model Considering Core Utilization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1210-1217 [Conf]
  3. Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
    Wire Length Distribution Model Considering Core Utilization for System on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:276-277 [Conf]
  4. Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu
    Prediction of delay time for future LSI using on-chip transmission line interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:7-12 [Conf]

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