The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tohru Ishihara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tohru Ishihara, Kunihiro Asada
    A system level memory power optimization technique using multiple supply and threshold voltages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:456-461 [Conf]
  2. Tohru Ishihara, Kunihiro Asada
    An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:282-287 [Conf]
  3. Tohru Ishihara, Hiroto Yasuura
    Power-Pro: Programmable Power Management Architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:321-322 [Conf]
  4. Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara
    A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:268-273 [Conf]
  5. Tohru Ishihara, Farzan Fallah
    A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:358-363 [Conf]
  6. Tohru Ishihara, Hiroto Yasuura
    A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:617-616 [Conf]
  7. Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
    Instruction Scheduling for Power Reduction in Processor-Based System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:855-860 [Conf]
  8. Tohru Ishihara, Farzan Fallah
    A cache-defect-aware code placement algorithm for improving the performance of processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:995-1001 [Conf]
  9. Koji Inoue, Tohru Ishihara, Kazuaki Murakami
    Way-predicting set-associative cache for high performance and low energy consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:273-275 [Conf]
  10. Tohru Ishihara, Farzan Fallah
    A non-uniform cache architecture for low power system design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:363-368 [Conf]
  11. Tohru Ishihara, Hiroto Yasuura
    Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:117-120 [Conf]
  12. Tohru Ishihara, Hiroto Yasuura
    Voltage scheduling problem for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:197-202 [Conf]
  13. Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto
    A Simulation-Based Soft Error Estimation Methodology for Computer Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:196-203 [Conf]
  14. Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
    Real-Time Task Scheduling for a Variable Voltage Processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:24-29 [Conf]
  15. Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
    Comparative Study On Verilog-Based And C-Based Hardware Design Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:41-42 [Conf]
  16. Tohru Ishihara, Kunihiro Asada
    An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:282-287 [Conf]
  17. Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
    A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:268-273 [Conf]
  18. Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
    Software Energy Reduction Techniques for Variable-Voltage Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:31-41 [Journal]
  19. Tohru Ishihara, Masakazu Kojima
    On the big Mu in the affine scaling algorithm. [Citation Graph (0, 0)][DBLP]
    Math. Program., 1993, v:62, n:, pp:85-93 [Journal]
  20. Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
    Task scheduling for reliable cache architectures of multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1490-1495 [Conf]
  21. Tohru Ishihara, Farzan Fallah
    A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  22. A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. [Citation Graph (, )][DBLP]


  23. Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. [Citation Graph (, )][DBLP]


  24. Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. [Citation Graph (, )][DBLP]


  25. An Energy Characterization Framework for Software-Based Embedded Systems. [Citation Graph (, )][DBLP]


  26. A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  27. Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. [Citation Graph (, )][DBLP]


  28. Simultaneous optimization of memory configuration and code allocation for low power embedded systems. [Citation Graph (, )][DBLP]


  29. Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. [Citation Graph (, )][DBLP]


  30. Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. [Citation Graph (, )][DBLP]


  31. Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. [Citation Graph (, )][DBLP]


  32. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. [Citation Graph (, )][DBLP]


  33. AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. [Citation Graph (, )][DBLP]


Search in 0.121secs, Finished in 0.122secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002