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Yi-Min Jiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho
    A Hybrid Power Model for RTL Power Estimation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:551-556 [Conf]
  2. Yi-Min Jiang, Kwang-Ting Cheng
    Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:760-765 [Conf]
  3. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
    Post-Layout Logic Restructuring for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:662-665 [Conf]
  4. Yi-Min Jiang, Kwang-Ting Cheng
    Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:698-0 [Conf]
  5. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:493-496 [Conf]
  6. Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
    Estimation of maximum power supply noise for deep sub-micron designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:233-238 [Conf]
  7. Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng
    VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:156-161 [Conf]
  8. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:137-144 [Conf]
  9. Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
    HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:307-312 [Conf]
  10. Kaijian Shi, Zhian Lin, Yi-Min Jiang
    A Power Network Synthesis Method for Industrial Power Gating Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:362-367 [Conf]
  11. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Delay testing considering power supply noise effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:181-190 [Conf]
  12. Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
    Delay testing considering crosstalk-induced effects. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:558-567 [Conf]
  13. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
    Performance-driven interconnection optimization for microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:137-149 [Journal]
  14. Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:416-425 [Journal]
  15. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:756-769 [Journal]
  16. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Estimation for maximum instantaneous current through supply lines for CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:61-73 [Journal]
  17. Yi-Min Jiang, Kwang-Ting Cheng
    Vector generation for power supply noise estimation and verification of deep submicron designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:329-340 [Journal]

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