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Title:
Author:
Yehea I. Ismail: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ja Chun Ku, Yehea I. Ismail
    Area optimization for leakage reduction and thermal stability in nanometer scale technologies. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:231-236 [Conf]
  2. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable RLCK circuit crunching. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:226-231 [Conf]
  3. Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
    Piece-wise approximations of RLCK circuit responses using moment matching. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:927-932 [Conf]
  4. Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
    Statistical static timing analysis: how simple can we get? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:652-657 [Conf]
  5. Maged Ghoneima, Yehea I. Ismail
    Optimum positioning of interleaved repeaters In bidirectional buses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:586-591 [Conf]
  6. Frank Huebbers, Ali Dasdan, Yehea I. Ismail
    Computation of accurate interconnect process parameter values for performance corners under process variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:797-800 [Conf]
  7. Yehea I. Ismail, Eby G. Friedman
    Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:721-724 [Conf]
  8. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Figures of Merit to Characterize the Importance of On-Chip Inductance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:560-565 [Conf]
  9. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Equivalent Elmore Delay for RLC Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:715-720 [Conf]
  10. Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
    Efficient model order reduction including skin effect. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:232-237 [Conf]
  11. Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
    Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:770-779 [Conf]
  12. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:39-44 [Conf]
  13. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:56-59 [Conf]
  14. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Power density minimization for highly-associative caches in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:100-104 [Conf]
  15. Noha Mahmoud, Maged Ghoneima, Yehea I. Ismail
    Physical limitations on the bit-rate of on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:13-19 [Conf]
  16. Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
    NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:25-30 [Conf]
  17. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Weibull Based Analytical Waveform Model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:161-168 [Conf]
  18. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Modeling unbuffered latches for timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:254-260 [Conf]
  19. Maged Ghoneima, Yehea I. Ismail
    Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:800-807 [Conf]
  20. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:541-546 [Conf]
  21. Yehea I. Ismail
    Efficient model order reduction via multi-node moment matching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:767-774 [Conf]
  22. Yehea I. Ismail, Chirayu S. Amin
    Computation of signal threshold crossing times directly from higher order moments. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:246-253 [Conf]
  23. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Repeater insertion in tree structured inductive interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:420-424 [Conf]
  24. Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Expanding the frequency range of AWE via time shifting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:935-938 [Conf]
  25. Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
    A timing dependent power estimation framework considering coupling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:401-407 [Conf]
  26. Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
    Importance of volume discretization of single and coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:119-126 [Conf]
  27. Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
    A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:253-257 [Conf]
  28. Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Realizable reduction of RLC circuits using node elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:494-497 [Conf]
  29. Daniel Dai, Yehea I. Ismail, Wei Wang, Hanif M. Ladak
    Powder-based fabrication techniques for single-wall carbon nanotube circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:701-704 [Conf]
  30. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
    Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:592-595 [Conf]
  31. Noha H. Mahmoud, Yehea I. Ismail
    Accurate rise time and overshoots estimation in RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:477-480 [Conf]
  32. Shizhong Mei, Yehea I. Ismail
    Modeling skin effect with reduced decoupled R-L circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:588-591 [Conf]
  33. Yehea I. Ismail, Eby G. Friedman
    Repeater insertion in RLC lines for minimum propagation delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:404-407 [Conf]
  34. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Signal waveform characterization in RLC trees. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:190-193 [Conf]
  35. Maged Ghoneima, Yehea I. Ismail
    Low power coupling-based encoding for on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:325-328 [Conf]
  36. Maged Ghoneima, Yehea I. Ismail
    Effect of relative delay on the dissipated energy in coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:525-528 [Conf]
  37. Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:197-200 [Conf]
  38. Yehea I. Ismail
    Evaluating noise pulses in RC networks due to capacitive coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:653-656 [Conf]
  39. Maged Ghoneima, Yehea I. Ismail
    Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:66-69 [Conf]
  40. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Power dissipated by CMOS gates driving lossless transmission lines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:139-142 [Conf]
  41. Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
    Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:79-84 [Conf]
  42. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the Data Switching Activity on Serial Link Buses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:425-432 [Conf]
  43. Masud H. Chowdhury, Yehea I. Ismail
    Analysis of Coupling Noise in Dynamic Circuit. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:320-325 [Conf]
  44. Masud H. Chowdhury, Yehea I. Ismail
    Possible Noise Failure Modes in Static and Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:123-126 [Conf]
  45. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:283-293 [Conf]
  46. Yehea I. Ismail, Eby G. Friedman
    On the Extraction of On-Chip Inductance. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:31-40 [Journal]
  47. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:305-0 [Journal]
  48. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable reduction of interconnect circuits including self and mutual inductances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:271-277 [Journal]
  49. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Weibull-based analytical waveform model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1156-1168 [Journal]
  50. Maged Ghoneima, Yehea I. Ismail
    Optimum positioning of interleaved repeaters in bidirectional buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:461-469 [Journal]
  51. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:821-836 [Journal]
  52. Yehea I. Ismail, Chirayu S. Amin
    Computation of signal-threshold crossing times directly from higher order moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1264-1276 [Journal]
  53. Yehea I. Ismail, Eby G. Friedman
    DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:131-144 [Journal]
  54. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Equivalent Elmore delay for RLC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:83-97 [Journal]
  55. Maged Ghoneima, Yehea I. Ismail
    Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1348-1359 [Journal]
  56. Shizhong Mei, Yehea I. Ismail
    Modeling skin and proximity effects with reduced realizable RL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:437-447 [Journal]
  57. Masud H. Chowdhury, Yehea I. Ismail
    Realistic scalability of noise in dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:637-641 [Journal]
  58. Ja Chun Ku, Yehea I. Ismail
    Attaining Thermal Integrity in Nanometer Chips. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3223-3226 [Conf]
  59. DiaaEldin Khalil, Yehea I. Ismail
    Approximate Frequency Response Models for RLC Power Grids. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3784-3787 [Conf]
  60. Ja Chun Ku, Yehea I. Ismail
    A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3736-3739 [Conf]
  61. Ahmed Shebaita, Yehea I. Ismail
    Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1385-1388 [Conf]
  62. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the data switching activity of serialized datastreams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  63. DiaaEldin Khalil, Yehea I. Ismail
    Optimum sizing of power grids for IR drop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  64. Ja Chun Ku, Yehea I. Ismail
    Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:963-970 [Journal]
  65. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:592-604 [Journal]
  66. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Figures of merit to characterize the importance of on-chip inductance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:442-449 [Journal]
  67. Yehea I. Ismail, Eby G. Friedman
    Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:195-206 [Journal]
  68. Yehea I. Ismail, Eby G. Friedman, J. L. Neves
    Exploiting the on-chip inductance in high-speed clock distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:963-973 [Journal]
  69. Yehea I. Ismail, Byron Krauter
    Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:683-684 [Journal]
  70. Yehea I. Ismail
    On-chip inductance cons and pros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:685-694 [Journal]
  71. Yehea I. Ismail
    Improved model-order reduction by using spacial information in moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:900-908 [Journal]

  72. A self-adjusting clock tree architecture to cope with temperature variations. [Citation Graph (, )][DBLP]


  73. Multi-layer interconnect performance corners for variation-aware timing analysis. [Citation Graph (, )][DBLP]


  74. Including inductance in static timing analysis. [Citation Graph (, )][DBLP]


  75. FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. [Citation Graph (, )][DBLP]


  76. Accurate decoupling of capacitively coupled buses. [Citation Graph (, )][DBLP]


  77. Power-supply-variation-aware timing analysis of synchronous systems. [Citation Graph (, )][DBLP]


  78. Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. [Citation Graph (, )][DBLP]


  79. Interconnect design and limitations in nanoscale technologies. [Citation Graph (, )][DBLP]


  80. Thermal-aware methodology for repeater insertion in low-power VLSI circuits. [Citation Graph (, )][DBLP]


  81. Modeling and Characterizing Power Variability in Multicore Architectures. [Citation Graph (, )][DBLP]


  82. Analytical Model for the Propagation Delay of Through Silicon Vias. [Citation Graph (, )][DBLP]


  83. Variable latency caches for nanoscale processor. [Citation Graph (, )][DBLP]


  84. A global interconnect link design for many-core microprocessors. [Citation Graph (, )][DBLP]


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