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Jin-Fu Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin-Fu Li
    Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:65-70 [Conf]
  2. Jin-Fu Li, Chao-Da Huang
    An Efficient Diagnosis Scheme for Random Access Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:277-282 [Conf]
  3. Jin-Fu Li, Chih-Chiang Hsu
    Efficient Test Methodologies for Conditional Sum Adders. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:319-324 [Conf]
  4. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
    A built-in self-test and self-diagnosis scheme for embedded SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:45-50 [Conf]
  5. Jin-Fu Li, Cheng-Wen Wu
    Memory fault diagnosis by syndrome compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:97-101 [Conf]
  6. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Ping Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Scheme for System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:486-490 [Conf]
  7. Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
    An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:574-579 [Conf]
  8. Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
    A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:53-58 [Conf]
  9. Jin-Fu Li, Cheng-Wen Wu
    Testable and Fault Tolerant Design for FFT Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:201-209 [Conf]
  10. Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li
    A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:362-370 [Conf]
  11. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:262-0 [Conf]
  12. Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang
    A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:77-80 [Conf]
  13. Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    March-based RAM diagnosis algorithms for stuck-at and coupling faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:758-767 [Conf]
  14. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
    A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:393-402 [Conf]
  15. Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
    A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:53-0 [Conf]
  16. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:68-0 [Conf]
  17. Jin-Fu Li, Chou-Kun Lin
    Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:60-65 [Conf]
  18. Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
    Testing and Diagnosing Embedded Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:389-394 [Conf]
  19. Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen
    A Built-In Self-Repair Scheme for Multiport RAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:355-360 [Conf]
  20. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Methodology for Systems on Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:69-81 [Journal]
  21. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
    A built-in self-repair design for RAMs with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:742-745 [Journal]
  22. Yu-Jen Huang, Jin-Fu Li
    Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:55-62 [Conf]
  23. Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
    An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  24. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
    Built-in redundancy analysis for memory yield improvement. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:386-399 [Journal]
  25. Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng
    ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1135-1143 [Journal]
  26. Jin-Fu Li, Cheng-Wen Wu
    Efficient FFT network testing and diagnosis schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:267-278 [Journal]

  27. Testability Exploration of 3-D RAMs and CAMs. [Citation Graph (, )][DBLP]


  28. Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. [Citation Graph (, )][DBLP]


  29. Efficient diagnosis algorithms for drowsy SRAMs. [Citation Graph (, )][DBLP]


  30. A low-cost and scalable test architecture for multi-core chips. [Citation Graph (, )][DBLP]


  31. A low-cost built-in self-test scheme for an array of memories. [Citation Graph (, )][DBLP]


  32. Raisin: Redundancy Analysis Algorithm Simulation. [Citation Graph (, )][DBLP]


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