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Hannah Honghua Yang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
    Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:8-15 [Conf]
  2. Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie
    A Theoretical Upper Bound for IP-Based Floorplanning. [Citation Graph (0, 0)][DBLP]
    COCOON, 2005, pp:411-419 [Conf]
  3. Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
    Multilevel floorplanning/placement for large-scale modules using B*-trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:812-817 [Conf]
  4. Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
    Faster and more accurate wiring evaluation in interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:62-67 [Conf]
  5. Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning and interconnect planning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:354-357 [Conf]
  6. Hannah Honghua Yang, D. F. Wong
    Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:150-155 [Conf]
  7. Hannah Honghua Yang, D. F. Wong
    New algorithms for min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:216-222 [Conf]
  8. Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
    Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:81-84 [Conf]
  9. Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
    Constrained "Modern" Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:128-135 [Conf]
  10. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng
    Integrating dynamic thermal via planning with 3D floorplanning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:178-185 [Conf]
  11. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:56-61 [Conf]
  12. Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman
    Logic Verification of Very Large Circuits Using Shark. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:310-317 [Conf]
  13. Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
    Constrained floorplanning using network flows. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:572-580 [Journal]
  14. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:730-741 [Journal]
  15. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:272-278 [Journal]
  16. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:800-807 [Journal]
  17. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with boundary constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1385-1389 [Journal]
  18. Hannah Honghua Yang, Martin D. F. Wong
    Balanced partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1533-1540 [Journal]
  19. Hannah Honghua Yang, Martin D. F. Wong
    Circuit clustering for delay minimization under area and pin constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:976-986 [Journal]
  20. Hannah Honghua Yang, Martin D. F. Wong
    Optimal min-area min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1175-1183 [Journal]
  21. Zuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
    Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:325-345 [Journal]

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