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Publications of Author

1. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
   An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:323-326 [Conf]
   
2. Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
   An efficient design-for-verification technique for HDLs. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:103-108 [Conf]
   
3. Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu
   A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:164-169 [Conf]
   
4. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
   Effective Error Diagnosis for RTL Designs in HDLs. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:362-367 [Conf]
   
5. Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu
   An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:286-290 [Conf]
   
6. Chien-Nan Jimmy Liu, Jing-Yang Jou
   An Efficient Functional Coverage Test for HDL Descriptions at RTL. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:325-327 [Conf]
   
7. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing Ya Jou
   Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:5682-5685 [Conf]
   
8. Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
   Automatic Functional Vector Generation Using the Interacting FSM Model. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:372-377 [Conf]
   
9. Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu
   A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:543-552 [Conf]
   
10. Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
    A Design-for-Verification Technique for Functional Pattern Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:48-55 [Journal]
    
11. Chien-Nan Jimmy Liu, Jing-Yang Jou
    An Automatic Controller Extractor for HDL Descriptions at the RTL. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:72-77 [Journal]
    
12. Wei-Hsiang Cheng, Chin-Lung Chuang, Chien-Nan Jimmy Liu
    An efficient mechanism to provide full visibility for hardware debugging. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
13. Chin-Cheng Kuo, Chien-Nan Jimmy Liu
    On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:116-121 [Conf]
    
14. Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou
    A Tableless Approach for High-Level Power Modeling Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:1, pp:71-90 [Journal]
    
15. 
    On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. [Citation Graph (, )][DBLP]
    
    
16. 
    A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. [Citation Graph (, )][DBLP]
    
    
17. 
    Behavior-level yield enhancement approach for large-scaled analog circuits. [Citation Graph (, )][DBLP]
    
    
18. 
    Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. [Citation Graph (, )][DBLP]
    
    
19. 
    Quick supply current waveform estimation at gate level using existed cell library information. [Citation Graph (, )][DBLP]
    
    
20. 
    A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. [Citation Graph (, )][DBLP]
    
    
21. 
    Hybrid Approach to Faster Functional Verification with Full Visibility. [Citation Graph (, )][DBLP]