The SCEAS System
| |||||||

## Search the dblp DataBase
Zhuo Li:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Zhuo Li, Weiping Shi
**An**[Citation Graph (0, 0)][DBLP]*O*(*mn*) time algorithm for optimal buffer insertion of nets with*m*sinks. ASP-DAC, 2006, pp:320-325 [Conf] - Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
**Making fast buffer insertion even faster via approximation techniques.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:13-18 [Conf] - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
**Longest path selection for delay test under process variation.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:98-103 [Conf] - Weiping Shi, Zhuo Li, Charles J. Alpert
**Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:609-614 [Conf] - Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
**Fast algorithms for slew constrained minimum cost buffering.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:308-313 [Conf] - Weiping Shi, Zhuo Li
**An O(nlogn) time algorithm for optimal buffer insertion.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:580-585 [Conf] - Mandar Waghmode, Zhuo Li, Weiping Shi
**Buffer insertion in large circuits with constructive solution search techniques.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:296-301 [Conf] - Zhuo Li, Weiping Shi
**An O(bn**[Citation Graph (0, 0)][DBLP]^{2}) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. DATE, 2005, pp:1324-1329 [Conf] - Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
**CodSim -- A Combined Delay Fault Simulator.**[Citation Graph (0, 0)][DBLP] DFT, 2003, pp:79-0 [Conf] - Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
**A new RLC buffer insertion algorithm.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:553-557 [Conf] - Zhuo Li, Kin-Man Lam, Lansun Shen
**Rate control for MPEG-4 FGS coded video using piecewise rate distortion model.**[Citation Graph (0, 0)][DBLP] ICME, 2004, pp:153-156 [Conf] - Zhuo Li, Xiang Lu, Weiping Shi
**Process variation dimension reduction based on SVD.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:672-675 [Conf] - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
**PARADE: PARAmetric Delay Evaluation under Process Variation.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:276-280 [Conf] - Sani R. Nassif, Zhuo Li
**A More Effective C**[Citation Graph (0, 0)][DBLP]_{EFF}. ISQED, 2005, pp:648-653 [Conf] - Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
**Probabilistic Congestion Prediction with Partial Blockages.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:841-846 [Conf] - Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
**K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.**[Citation Graph (0, 0)][DBLP] ITC, 2004, pp:223-231 [Conf] - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
**A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.**[Citation Graph (0, 0)][DBLP] MTV, 2004, pp:97-102 [Conf] - Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
**A Circuit Level Fault Model for Resistive Opens and Bridges.**[Citation Graph (0, 0)][DBLP] VTS, 2003, pp:379-384 [Conf] - Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
**A Statistical Fault Coverage Metric for Realistic Path Delay Faults.**[Citation Graph (0, 0)][DBLP] VTS, 2004, pp:37-42 [Conf] - Zhenheng Li, Zhuo Li, You'an Cao
**Enumeration of symplectic and orthogonal injective partial transformations.**[Citation Graph (0, 0)][DBLP] Discrete Mathematics, 2006, v:306, n:15, pp:1781-1787 [Journal] - Zhuo Li, Weiping Shi
**An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:484-489 [Journal] - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
**Longest-path selection for delay test under process variation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1924-1929 [Journal] - Weiping Shi, Zhuo Li
**A fast algorithm for optimal buffer insertion.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:879-891 [Journal] - Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
**A circuit level fault model for resistive bridges.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:546-559 [Journal] - Ying Zhou, Zhuo Li, Weiping Shi
**Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:835-840 [Conf] - Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
**The nuts and bolts of physical synthesis.**[Citation Graph (0, 0)][DBLP] SLIP, 2007, pp:89-94 [Conf] - Zhuo Li, Weiping Shi
**An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] **A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.**[Citation Graph (, )][DBLP]**Path smoothing via discrete optimization.**[Citation Graph (, )][DBLP]**A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.**[Citation Graph (, )][DBLP]**Detecting tangled logic structures in VLSI netlists.**[Citation Graph (, )][DBLP]**Pyramids: an efficient computational geometry-based approach for timing-driven placement.**[Citation Graph (, )][DBLP]**A polynomial time approximation scheme for timing constrained minimum cost layer assignment.**[Citation Graph (, )][DBLP]**A Location-free Prediction-based Sleep Scheduling Protocol for Object Tracking in Sensor Networks.**[Citation Graph (, )][DBLP]**RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.**[Citation Graph (, )][DBLP]**Fast interconnect synthesis with layer assignment.**[Citation Graph (, )][DBLP]**What makes a design difficult to route.**[Citation Graph (, )][DBLP]**A faster approximation scheme for timing driven minimum cost layer assignment.**[Citation Graph (, )][DBLP]**ITOP: integrating timing optimization within placement.**[Citation Graph (, )][DBLP]**Ultra-fast interconnect driven cell cloning for minimizing critical path delay.**[Citation Graph (, )][DBLP]**A Root-Finding Method for Assessing SRAM Stability.**[Citation Graph (, )][DBLP]**The impact of BEOL lithography effects on the SRAM cell performance and yield.**[Citation Graph (, )][DBLP]**Proportion-Integral Power Control for Wireless Ad Hoc Networks.**[Citation Graph (, )][DBLP]**On Handoff Minimization in Wireless Networks: From a Navigation Perspective.**[Citation Graph (, )][DBLP]**On accuracy of region based localization algorithms for wireless sensor networks.**[Citation Graph (, )][DBLP]**A family of asymptotically good quantum codes based on code concatenation**[Citation Graph (, )][DBLP]**No More Perfect Codes: Classification of Perfect Quantum Codes**[Citation Graph (, )][DBLP]
Search in 0.003secs, Finished in 0.004secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |