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Zhuo Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhuo Li, Weiping Shi
    An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:320-325 [Conf]
  2. Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:13-18 [Conf]
  3. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:98-103 [Conf]
  4. Weiping Shi, Zhuo Li, Charles J. Alpert
    Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:609-614 [Conf]
  5. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  6. Weiping Shi, Zhuo Li
    An O(nlogn) time algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:580-585 [Conf]
  7. Mandar Waghmode, Zhuo Li, Weiping Shi
    Buffer insertion in large circuits with constructive solution search techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:296-301 [Conf]
  8. Zhuo Li, Weiping Shi
    An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1324-1329 [Conf]
  9. Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
    CodSim -- A Combined Delay Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:79-0 [Conf]
  10. Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
    A new RLC buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:553-557 [Conf]
  11. Zhuo Li, Kin-Man Lam, Lansun Shen
    Rate control for MPEG-4 FGS coded video using piecewise rate distortion model. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:153-156 [Conf]
  12. Zhuo Li, Xiang Lu, Weiping Shi
    Process variation dimension reduction based on SVD. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:672-675 [Conf]
  13. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    PARADE: PARAmetric Delay Evaluation under Process Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:276-280 [Conf]
  14. Sani R. Nassif, Zhuo Li
    A More Effective CEFF. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:648-653 [Conf]
  15. Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
    Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:841-846 [Conf]
  16. Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
    K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:223-231 [Conf]
  17. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:97-102 [Conf]
  18. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A Circuit Level Fault Model for Resistive Opens and Bridges. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:379-384 [Conf]
  19. Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
    A Statistical Fault Coverage Metric for Realistic Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:37-42 [Conf]
  20. Zhenheng Li, Zhuo Li, You'an Cao
    Enumeration of symplectic and orthogonal injective partial transformations. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 2006, v:306, n:15, pp:1781-1787 [Journal]
  21. Zhuo Li, Weiping Shi
    An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:484-489 [Journal]
  22. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest-path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1924-1929 [Journal]
  23. Weiping Shi, Zhuo Li
    A fast algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:879-891 [Journal]
  24. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A circuit level fault model for resistive bridges. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:546-559 [Journal]
  25. Ying Zhou, Zhuo Li, Weiping Shi
    Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:835-840 [Conf]
  26. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]
  27. Zhuo Li, Weiping Shi
    An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  28. A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. [Citation Graph (, )][DBLP]


  29. Path smoothing via discrete optimization. [Citation Graph (, )][DBLP]


  30. A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. [Citation Graph (, )][DBLP]


  31. Detecting tangled logic structures in VLSI netlists. [Citation Graph (, )][DBLP]


  32. Pyramids: an efficient computational geometry-based approach for timing-driven placement. [Citation Graph (, )][DBLP]


  33. A polynomial time approximation scheme for timing constrained minimum cost layer assignment. [Citation Graph (, )][DBLP]


  34. A Location-free Prediction-based Sleep Scheduling Protocol for Object Tracking in Sensor Networks. [Citation Graph (, )][DBLP]


  35. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]


  36. Fast interconnect synthesis with layer assignment. [Citation Graph (, )][DBLP]


  37. What makes a design difficult to route. [Citation Graph (, )][DBLP]


  38. A faster approximation scheme for timing driven minimum cost layer assignment. [Citation Graph (, )][DBLP]


  39. ITOP: integrating timing optimization within placement. [Citation Graph (, )][DBLP]


  40. Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]


  41. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]


  42. The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]


  43. Proportion-Integral Power Control for Wireless Ad Hoc Networks. [Citation Graph (, )][DBLP]


  44. On Handoff Minimization in Wireless Networks: From a Navigation Perspective. [Citation Graph (, )][DBLP]


  45. On accuracy of region based localization algorithms for wireless sensor networks. [Citation Graph (, )][DBLP]


  46. A family of asymptotically good quantum codes based on code concatenation [Citation Graph (, )][DBLP]


  47. No More Perfect Codes: Classification of Perfect Quantum Codes [Citation Graph (, )][DBLP]


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