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Title:
Author:
Weiping Shi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhuo Li, Weiping Shi
    An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:320-325 [Conf]
  2. Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:13-18 [Conf]
  3. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:98-103 [Conf]
  4. Weiping Shi, Zhuo Li, Charles J. Alpert
    Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:609-614 [Conf]
  5. Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
    Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:354-359 [Conf]
  6. Sheila A. Greibach, Weiping Shi, Shai Simonson
    Single Tree Grammars. [Citation Graph (0, 0)][DBLP]
    Theoretical Studies in Computer Science, 1992, pp:73-99 [Conf]
  7. Qiushuang Wang, Beijie Luo, Guang Zhi, Dangsheng Huang, Yong Xu, Weiping Shi
    The clinical evaluation of the modern technology of computer in echocardiography. [Citation Graph (0, 0)][DBLP]
    CARS, 2003, pp:1401- [Conf]
  8. Farhad Shahrokhi, Weiping Shi
    Efficient Deterministic Algorithms for Embedding Graphs on Books. [Citation Graph (0, 0)][DBLP]
    COCOON, 1996, pp:162-168 [Conf]
  9. Weiping Shi, Douglas B. West
    Optimal Algorithms for Finding Connected Components of an Unknown Graph. [Citation Graph (0, 0)][DBLP]
    COCOON, 1995, pp:131-140 [Conf]
  10. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  11. Peng Li, Weiping Shi
    Model order reduction of linear networks with massive ports via frequency-dependent port packing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:267-272 [Conf]
  12. Hemant Mahawar, Vivek Sarin, Weiping Shi
    A solenoidal basis method for efficient inductance extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:751-756 [Conf]
  13. Weiping Shi, Zhuo Li
    An O(nlogn) time algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:580-585 [Conf]
  14. Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu
    A Fast Hierarchical Algorithm for 3-D Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:212-217 [Conf]
  15. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Path based buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:509-514 [Conf]
  16. Mandar Waghmode, Zhuo Li, Weiping Shi
    Buffer insertion in large circuits with constructive solution search techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:296-301 [Conf]
  17. Shu Yan, Vivek Sarin, Weiping Shi
    Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:788-793 [Conf]
  18. Zhuo Li, Weiping Shi
    An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1324-1329 [Conf]
  19. Weiping Shi
    A General Method to Design and Reconfigure Loop-Based Linear Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:221-229 [Conf]
  20. Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
    CodSim -- A Combined Delay Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:79-0 [Conf]
  21. Weiping Shi, Douglas B. West
    Optimal Structural Diagnosis of Wiring Networks. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:162-171 [Conf]
  22. Weiping Shi
    An optimal algorithm for area minimization of slicing floorplans. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:480-484 [Conf]
  23. Peichen Pan, Weiping Shi, C. L. Liu
    Area minimization for hierarchical floorplans. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:436-440 [Conf]
  24. Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
    A new RLC buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:553-557 [Conf]
  25. Hemant Mahawar, Vivek Sarin, Weiping Shi
    Fast Inductance Extraction of Large VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  26. Zhuo Li, Xiang Lu, Weiping Shi
    Process variation dimension reduction based on SVD. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:672-675 [Conf]
  27. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    PARADE: PARAmetric Delay Evaluation under Process Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:276-280 [Conf]
  28. Fangqing Yu, Weiping Shi
    A Divide-and-Conquer Algorithm for 3D Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:253-258 [Conf]
  29. Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
    Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:841-846 [Conf]
  30. Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi
    An Efficient Algorithm for RLC Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:171-175 [Conf]
  31. Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
    K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:223-231 [Conf]
  32. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:97-102 [Conf]
  33. Wangqi Qiu, Weiping Shi
    Minimum moment Steiner trees. [Citation Graph (0, 0)][DBLP]
    SODA, 2004, pp:488-495 [Conf]
  34. Weiping Shi, Chen Su
    The rectilinear Steiner arborescence problem is NP-complete. [Citation Graph (0, 0)][DBLP]
    SODA, 2000, pp:780-787 [Conf]
  35. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A Circuit Level Fault Model for Resistive Opens and Bridges. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:379-384 [Conf]
  36. Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
    A Statistical Fault Coverage Metric for Realistic Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:37-42 [Conf]
  37. Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker
    Static Compaction of Delay Tests Considering Power Supply Noise. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:235-240 [Conf]
  38. Peichen Pan, Weiping Shi, C. L. Liu
    Area Minimization for Hierarchical Floorplans. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1996, v:15, n:6, pp:550-571 [Journal]
  39. Farhad Shahrokhi, Weiping Shi
    On Crossing Sets, Disjoint Sets, and Pagenumber. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 2000, v:34, n:1, pp:40-53 [Journal]
  40. Herbert Edelsbrunner, Weiping Shi
    An O(n log² h) Time Algorithm for the Three-Dimensional Convex Hull Problem. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1991, v:20, n:2, pp:259-269 [Journal]
  41. Weiping Shi, Chen Su
    The Rectilinear Steiner Arborescence Problem Is NP-Complete. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 2005, v:35, n:3, pp:729-740 [Journal]
  42. Weiping Shi, Douglas B. West
    Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1999, v:28, n:5, pp:1541-1551 [Journal]
  43. Weiping Shi, Douglas B. West
    Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 2001, v:14, n:4, pp:510-523 [Journal]
  44. Ming-Feng Chang, Weiping Shi, W. Kent Fuchs
    Optimal Diagnosis Procedures for k-out-of-n Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:559-564 [Journal]
  45. Weiping Shi, Ming-Feng Chang, W. Kent Fuchs
    Harvest Rate of Reconfigurable Pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1200-1203 [Journal]
  46. Zhuo Li, Weiping Shi
    An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:484-489 [Journal]
  47. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest-path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1924-1929 [Journal]
  48. Weiping Shi
    A fast algorithm for area minimization of slicing floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1525-1532 [Journal]
  49. Weiping Shi, W. Kent Fuchs
    Probabilistic analysis and algorithms for reconfiguration of memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1153-1160 [Journal]
  50. Weiping Shi, Zhuo Li
    A fast algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:879-891 [Journal]
  51. Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu
    A fast hierarchical algorithm for three-dimensional capacitanceextraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:330-336 [Journal]
  52. Weiping Shi, Fangqing Yu
    A divide-and-conquer algorithm for 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1157-1163 [Journal]
  53. Shu Yan, Vivek Sarin, Weiping Shi
    Sparse transformations and preconditioners for 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1420-1426 [Journal]
  54. Shu Yan, Vivek Sarin, Weiping Shi
    Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2282-2286 [Journal]
  55. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A circuit level fault model for resistive bridges. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:546-559 [Journal]
  56. Ying Zhou, Zhuo Li, Weiping Shi
    Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:835-840 [Conf]
  57. Zhanyuan Jiang, Shiyan Hu, Weiping Shi
    A New Twisted Differential Line Structure in Global Bus Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:180-183 [Conf]
  58. Zhuo Li, Weiping Shi
    An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  59. Weiping Shi, W. Kent Fuchs
    Optimal interconnect diagnosis of wiring networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:430-436 [Journal]

  60. A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. [Citation Graph (, )][DBLP]


  61. Circuit-wise buffer insertion and gate sizing algorithm with scalability. [Citation Graph (, )][DBLP]


  62. Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method. [Citation Graph (, )][DBLP]


  63. An Efficient, Scalable Hardware Engine for Boolean SATisfiability. [Citation Graph (, )][DBLP]


  64. SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. [Citation Graph (, )][DBLP]


  65. Multi-scenario buffer insertion in multi-core processor designs. [Citation Graph (, )][DBLP]


  66. Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]


  67. Fast characterization of parameterized cell library. [Citation Graph (, )][DBLP]


  68. The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]


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