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Publications of Author

1. Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
   A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:115-120 [Conf]
   
2. Jinjun Xiong, Lei He
   Probabilistic congestion model considering shielding for crosstalk reduction. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:739-742 [Conf]
   
3. Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
   Constraint driven I/O planning and placement for chip-package co-design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:207-212 [Conf]
   
4. Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
   Criticality computation in parameterized statistical timing. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:63-68 [Conf]
   
5. Jinjun Xiong, Lei He
   Full-Chip Multilevel Routing for Power and Signal Integrity. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1116-1123 [Conf]
   
6. Jinjun Xiong, King Ho Tam, Lei He
   Buffer Insertion Considering Process Variation. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:970-975 [Conf]
   
7. Jinjun Xiong, Jun Chen, James Ma, Lei He
   Post global routing RLC crosstalk budgeting. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2002, pp:504-509 [Conf]
   
8. Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
   Performance and RLC crosstalk driven global routing. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:65-68 [Conf]
   
9. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
   Shielding area optimization under the solution of interconnect crosstalk. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:297-300 [Conf]
   
10. Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
    Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:78-85 [Conf]
    
11. Changbo Long, Jinjun Xiong, Lei He
    On optimal physical synthesis of sleep transistors. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:156-161 [Conf]
    
12. Jinjun Xiong, Lei He
    Fast buffer insertion considering process variations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:128-135 [Conf]
    
13. Jinjun Xiong, Vladimir Zolotov, Lei He
    Robust extraction of spatial correlation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:2-9 [Conf]
    
14. Jinjun Xiong, Lei He
    Full-chip routing optimization with RLC crosstalk budgeting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:366-377 [Journal]
    
15. Jinjun Xiong, Lei He
    Extended global routing with RLC crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:319-329 [Journal]
    
16. Lerong Cheng, Jinjun Xiong, Lei He
    Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:250-255 [Conf]
    
17. Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
    FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
    
18. Jinjun Xiong, Lei He
    Full-chip multilevel routing for power and signal integrity. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:226-234 [Journal]
    
19. 
    Incremental and on-demand random walk for iterative power distribution network analysis. [Citation Graph (, )][DBLP]
    
    
20. 
    Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. [Citation Graph (, )][DBLP]
    
    
21. 
    Static timing: Back to our roots. [Citation Graph (, )][DBLP]
    
    
22. 
    DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. [Citation Graph (, )][DBLP]
    
    
23. 
    Non-Gaussian statistical timing analysis using second-order polynomial fitting. [Citation Graph (, )][DBLP]
    
    
24. 
    Statistical ordering of correlated timing quantities and its application for path ranking. [Citation Graph (, )][DBLP]
    
    
25. 
    Statistical multilayer process space coverage for at-speed test. [Citation Graph (, )][DBLP]
    
    
26. 
    Transistor sizing of custom high-performance digital circuits with parametric yield considerations. [Citation Graph (, )][DBLP]
    
    
27. 
    A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation. [Citation Graph (, )][DBLP]
    
    
28. 
    Incremental Criticality and Yield Gradients. [Citation Graph (, )][DBLP]
    
    
29. 
    An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. [Citation Graph (, )][DBLP]
    
    
30. 
    Optimal Margin Computation for At-Speed Test. [Citation Graph (, )][DBLP]
    
    
31. 
    A linear statistical analysis for full-chip leakage power with spatial correlation. [Citation Graph (, )][DBLP]
    
    
32. 
    Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]
    
    
33. 
    Efficient decoupling capacitance budgeting considering operation and process variations. [Citation Graph (, )][DBLP]
    
    
34. 
    Compact modeling of variational waveforms. [Citation Graph (, )][DBLP]
    
    
35. 
    Statistical path selection for at-speed test. [Citation Graph (, )][DBLP]
    
    
36. 
    Voltage binning under process variation. [Citation Graph (, )][DBLP]
    
    
37. 
    Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. [Citation Graph (, )][DBLP]
    
    
38. 
    Techniques of Power-gating to Kill Sub-Threshold Leakage. [Citation Graph (, )][DBLP]