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Seok-Yoon Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seung-Ho Jung, Jong-Humn Baek, Seok-Yoon Kim
    Short circuit power estimation of static CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:545-550 [Conf]
  2. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
    On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:207-212 [Conf]
  3. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
    AWE macromodels of VLSI interconnect for circuit simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:64-70 [Conf]
  4. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage
    Domain Characterization of Transmission Line Models for Efficient Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:558-562 [Conf]
  5. Ki-Young Kim, Seung-Yong Kim, Seok-Yoon Kim
    An Efficient Delay Metric on RC Interconnects Under Saturated Ramp Inputs. [Citation Graph (0, 0)][DBLP]
    ICCSA (4), 2006, pp:612-621 [Conf]
  6. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
    Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:729-736 [Journal]
  7. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi
    Domain characterization of transmission line models and analyses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:184-193 [Journal]
  8. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
    Time-domain macromodels for VLSI interconnect analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1257-1270 [Journal]
  9. Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim
    An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:65-74 [Conf]

  10. Reducing the Far-end Crosstalk Using Advanced Guard Trace in PCB Transmission Lines. [Citation Graph (, )][DBLP]


  11. Analytic Models for Peak Current Computation in General Interconnect Circuits. [Citation Graph (, )][DBLP]


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