The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Wayne Wei-Ming Dai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai
    KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:379-384 [Conf]
  2. Hao Ji, Qingjian Yu, Wayne Wei-Ming Dai
    SPICE compatible circuit models for partial reluctance K. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:786-791 [Conf]
  3. Minqing Liu, Wayne Wei-Ming Dai
    Modeling and analysis of integrated spiral inductors for RF system-in-package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:211-216 [Conf]
  4. Fangyi Luo, Yongbo Jia, Wayne Wei-Ming Dai
    Yield-preferred via insertion based on novel geotopological technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:730-735 [Conf]
  5. Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
    Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:267-268 [Conf]
  6. Man-Fai Yu, Wayne Wei-Ming Dai
    Pin assignment and routing on a single-layer Pin Grid Array. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  7. Anru Wang, Wayne Wei-Ming Dai
    Area-IO DRAM/logic integration with system-in-a-package (SiP). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:893-896 [Conf]
  8. Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai, Yee L. Low, Kevin J. O'Conner, King L. Tai
    Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:205-210 [Conf]
  9. Wayne Wei-Ming Dai
    Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:717-719 [Conf]
  10. Wayne Wei-Ming Dai, Tal Dayan, David Staepelaere
    Topological Routing in SURF: Generating a Rubber-Band sketch. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:39-44 [Conf]
  11. Wayne Wei-Ming Dai, Raymond Kong, Masao Sato
    Routability of a Rubber-Band Sketch. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:45-48 [Conf]
  12. Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh
    A Dynamic and Efficient Representation of Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:376-384 [Conf]
  13. Haifang Liao, Wayne Wei-Ming Dai, Rui Wang, Fung-Yuel Chang
    S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:726-731 [Conf]
  14. Paul B. Morton, Wayne Wei-Ming Dai
    Crosstalk noise estimation for noise management. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:659-664 [Conf]
  15. Joe G. Xi, Wayne Wei-Ming Dai
    Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:491-496 [Conf]
  16. Joe G. Xi, Wayne Wei-Ming Dai
    Useful-Skew Clock Routing With Gate Sizing for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:383-388 [Conf]
  17. Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II
    Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:371-376 [Conf]
  18. Jinsong Zhao, Wayne Wei-Ming Dai, Sharad Kapur, David E. Long
    Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:224-229 [Conf]
  19. Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai
    A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:280-285 [Conf]
  20. Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai
    Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:339-340 [Conf]
  21. Joel Darnauer, Wayne Wei-Ming Dai
    A Method for Generating Random Circuits and Its Application to Routability Measurement. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:66-72 [Conf]
  22. Tsuyoshi Isshiki, Wayne Wei-Ming Dai
    High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:167-173 [Conf]
  23. Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai
    Design of FPGAs with Area I/O for Field Programmable MCM. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:17-23 [Conf]
  24. Tsuyoshi Isshiki, Wayne Wei-Ming Dai
    Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM). [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:373-384 [Conf]
  25. Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue
    Rubber Band Routing and Dynamic Data Representation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:52-55 [Conf]
  26. Wayne Wei-Ming Dai, Howard Kalter, Rob Roy, Wayne Wolf
    Critical technologies and methodologies for systems-on-chips (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:- [Conf]
  27. Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai
    How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:150-155 [Conf]
  28. Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai
    A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:381-386 [Conf]
  29. Maggie Zhiwei Kang, Wayne Wei-Ming Dai
    Arbitrary rectilinear block packing based on sequence pair. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:259-266 [Conf]
  30. Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin
    Delay bounded buffered tree construction for timing driven floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:707-712 [Conf]
  31. Haifang Liao, Wayne Wei-Ming Dai
    Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:412-417 [Conf]
  32. Haifang Liao, Wayne Wei-Ming Dai
    Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:704-709 [Conf]
  33. Minqing Liu, Tiejun Yu, Wayne Wei-Ming Dai
    Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:424-429 [Conf]
  34. Jeffrey Z. Su, Wayne Wei-Ming Dai
    Post-route optimization for improved yield using a rubber-band wiring model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:700-706 [Conf]
  35. Joe G. Xi, Wayne Wei-Ming Dai
    Jitter-tolerant clock routing in two-phase synchronous systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:316-320 [Conf]
  36. Qing Zhu, Wayne Wei-Ming Dai
    Perfect-balance planar clock routing with minimal path-length. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:473-476 [Conf]
  37. Man-Fai Yu, Wayne Wei-Ming Dai
    Single-layer fanout routing and routability analysis for Ball Grid Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:581-586 [Conf]
  38. Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai
    Interchangeable pin routing with application to package layout. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:668-673 [Conf]
  39. Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:153-157 [Conf]
  40. Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
    Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:628-633 [Conf]
  41. Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
    Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:594-598 [Conf]
  42. Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
    Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:18-24 [Conf]
  43. Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
    Transformation of min-max optimization to least-square estimation and application to interconnect design optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:664-670 [Conf]
  44. Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata
    Optimal single hop multiple bus networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2541-2544 [Conf]
  45. Haifang Liao, Rui Wang, Rajit Chandra, Wayne Wei-Ming Dai
    S-parameter based macro model of distributed-lumped networks using Pade approximation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2319-2322 [Conf]
  46. Maggie Zhiwei Kang, Wayne Wei-Ming Dai
    Topology constrained rectilinear block packing for layout reuse. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:179-186 [Conf]
  47. Paul B. Morton, Wayne Wei-Ming Dai
    An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:22-28 [Conf]
  48. Shuo Zhang, Wayne Wei-Ming Dai
    TEG: a new post-layout optimization method. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:62-67 [Conf]
  49. Anru Wang, Wayne Wei-Ming Dai
    Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP). [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:562-566 [Conf]
  50. Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai
    Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:229-234 [Conf]
  51. Wayne Wei-Ming Dai, Kwang-Ting (Tim) Cheng
    Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:7-0 [Journal]
  52. David Staepelaere, Jeffrey Jue, Tal Dayan, Wayne Wei-Ming Dai
    SURF: Rubber-Band Routing System for Multichip Modules. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:18-26 [Journal]
  53. Wayne Wei-Ming Dai
    Hierarchical placement and floorplanning in BEAR. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1335-1349 [Journal]
  54. Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh
    Routing Region Definition and Ordering Scheme for Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:189-197 [Journal]
  55. Wayne Wei-Ming Dai, Ernest S. Kuh
    Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:828-837 [Journal]
  56. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area minimization of power distribution network using efficient nonlinear programming techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1086-1094 [Journal]
  57. Shuo Zhang, Wayne Wei-Ming Dai
    TEG: a new post-layout optimization method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:446-456 [Journal]
  58. Qing Zhu, Wayne Wei-Ming Dai
    High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1106-1118 [Journal]
  59. Qing Zhu, Wayne Wei-Ming Dai
    Planar clock routing for high performance chip and package co-design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:210-226 [Journal]

Search in 0.006secs, Finished in 0.009secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002