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Xin Jia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xin Jia, Ranga Vemuri
    Using GALS architecture to reduce the impact of long wire delay on FPGA performance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1260-1263 [Conf]
  2. Xin Jia, Ranga Vemuri
    A Design Methodology for Self-Timed Event Logic Pipelines. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:475-479 [Conf]
  3. Xin Jia, Ranga Vemuri
    The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:291-292 [Conf]
  4. Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
    A Dynamically Reconfigurable Asynchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:836-841 [Conf]
  5. Xin Jia, Ranga Vemuri
    A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:287-292 [Conf]
  6. Xin Jia, Ranga Vemuri
    Studying a GALS FPGA architecture using a parameterized automatic design flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:688-693 [Conf]
  7. Xin Jia, Ranga Vemuri
    CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:251-256 [Conf]

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