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Sherief Reda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew B. Kahng, Sherief Reda
    Combinatorial group testing methods for the BIST diagnosis problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:113-116 [Conf]
  2. Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
    Power-aware placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:795-800 [Conf]
  3. Andrew B. Kahng, Sherief Reda
    Placement feedback: a concept and method for better min-cut placements. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:357-362 [Conf]
  4. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    Boosting: Min-Cut Placement with Improved Signal Delay. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1098-1103 [Conf]
  5. Sherief Reda, Alex Orailoglu
    Reducing Test Application Time Through Test Data Mutation Encoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:387-395 [Conf]
  6. Sherief Reda, A. Salem
    Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:122-126 [Conf]
  7. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    On legalization of row-based placements. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:214-219 [Conf]
  8. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Evaluation of Placement Techniques for DNA Probe Array Layout. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:262-269 [Conf]
  9. Andrew B. Kahng, Sherief Reda
    Intrinsic shortest path length: a new, accurate a priori wirelength estimator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:173-180 [Conf]
  10. Andrew B. Kahng, Sherief Reda, Qinke Wang
    Architecture and details of a high quality, large-scale analytical placer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:891-898 [Conf]
  11. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Design Flow Enhancements for DNA Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:116-0 [Conf]
  12. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  13. Andrew B. Kahng, Sherief Reda
    Evaluation of placer suboptimality via zero-change netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:208-215 [Conf]
  14. Andrew B. Kahng, Sherief Reda, Qinke Wang
    APlace: a general analytic placement framework. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:233-235 [Conf]
  15. Sherief Reda, Amit Chowdhary
    Effective linear programming based placement methods. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:186-191 [Conf]
  16. Sherief Reda, Rolf Drechsler, Alex Orailoglu
    On the Relation between SAT and BDDs for Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:394-399 [Conf]
  17. Andrew B. Kahng, Sherief Reda, Puneet Sharma
    On-Line Adjustable Buffering for Runtime Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:550-555 [Conf]
  18. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Engineering a scalable placement heuristic for DNA probe arrays. [Citation Graph (0, 0)][DBLP]
    RECOMB, 2003, pp:148-156 [Conf]
  19. Andrew B. Kahng, Sherief Reda
    A tale of two nets: studies of wirelength progression in physical design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:17-24 [Conf]
  20. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Border Length Minimization in DNA Array Design. [Citation Graph (0, 0)][DBLP]
    WABI, 2002, pp:435-448 [Conf]
  21. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Scalable Heuristics for Design of DNA Probe Arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Computational Biology, 2004, v:11, n:2/3, pp:429-447 [Journal]
  22. Andrew B. Kahng, Sherief Reda
    Match twice and stitch: a new TSP tour construction heuristic. [Citation Graph (0, 0)][DBLP]
    Oper. Res. Lett., 2004, v:32, n:6, pp:499-509 [Journal]
  23. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Computer-Aided Optimization of DNA Array Design and Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:2, pp:305-320 [Journal]
  24. Andrew B. Kahng, Sherief Reda
    New and improved BIST diagnosis methods from combinatorial Group testing theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:533-543 [Journal]
  25. Andrew B. Kahng, Sherief Reda
    Wirelength minimization for min-cut placements via placement feedback. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1301-1312 [Journal]
  26. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
    A Fast Hierarchical Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:678-691 [Journal]

  27. Within-die process variations: How accurately can they be statistically modeled? [Citation Graph (, )][DBLP]


  28. Spectral techniques for high-resolution thermal characterization with limited sensor data. [Citation Graph (, )][DBLP]


  29. Thermal monitoring of real processors: techniques for sensor allocation and full characterization. [Citation Graph (, )][DBLP]


  30. Consistent runtime thermal prediction and control through workload phase detection. [Citation Graph (, )][DBLP]


  31. Analyzing the impact of process variations on parametric measurements: Novel models and applications. [Citation Graph (, )][DBLP]


  32. High-performance, cost-effective heterogeneous 3D FPGA architectures. [Citation Graph (, )][DBLP]


  33. Central vs. distributed dynamic thermal management for multi-core processors: which one is better? [Citation Graph (, )][DBLP]


  34. High-performance, cost-effective heterogeneous 3D FPGA architectures. [Citation Graph (, )][DBLP]


  35. Strategies for improving the parametric yield and profits of 3D ICs. [Citation Graph (, )][DBLP]


  36. Hardware libraries: An architecture for economic acceleration in soft multi-core environments. [Citation Graph (, )][DBLP]


  37. Frequency and voltage planning for multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]


  38. Frequency planning for multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]


  39. Reducing the leakage and timing variability of 2D ICcs using 3D ICs. [Citation Graph (, )][DBLP]


  40. Post-silicon power characterization using thermal infrared emissions. [Citation Graph (, )][DBLP]


  41. Using circuit structural analysis techniques for networks in systems biology. [Citation Graph (, )][DBLP]


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