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Vivek Tiwari: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha
    Topological Analysis for Leakage Prediction of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:39-44 [Conf]
  2. Vivek Tiwari, Mike Tien-Chien Lee
    Power analysis of a 32-bit embedded microcontroller. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Mahadevamurty Nemani, Vivek Tiwari
    Macro-driven circuit design methodology for high-performance datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:661-666 [Conf]
  4. Vivek Tiwari, Pranav Ashar, Sharad Malik
    Technology Mapping for Lower Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:74-79 [Conf]
  5. Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez
    Reducing Power in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:732-737 [Conf]
  6. Ed Grochowski, David Ayers, Vivek Tiwari
    Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:7-16 [Conf]
  7. Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt
    System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:569-573 [Conf]
  8. Vivek Tiwari, Sharad Malik, Andrew Wolfe
    Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:384-390 [Conf]
  9. Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe
    A Split Data Cache for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:32-39 [Conf]
  10. David Brooks, Vivek Tiwari, Margaret Martonosi
    Wattch: a framework for architectural-level power analysis and optimizations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:83-94 [Conf]
  11. Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari
    Do our low-power tools have enough horse power? (panel session) (title only). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:149- [Conf]
  12. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    An architectural solution for the inductive noise problem due to clock-gating. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:255-257 [Conf]
  13. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:221-226 [Conf]
  14. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and low-power scheduling techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:110-115 [Conf]
  15. Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari
    A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:48-0 [Conf]
  16. Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha
    Topological Analysis for Leakage Prediction of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:39-44 [Conf]
  17. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    Inductive Noise Reduction at the Architectural Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:162-167 [Conf]
  18. Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
    Instruction Level Power Analysis and Optimization of Software. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:326-328 [Conf]
  19. Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez
    Dynamic Power Management for Microprocessors: A Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:185-192 [Conf]
  20. Ed Grochowski, David Ayers, Vivek Tiwari
    Microarchitectural dI/dt Control. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:40-47 [Journal]
  21. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1051-1060 [Journal]
  22. Vivek Tiwari, Sharad Malik, Andrew Wolfe
    Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:437-445 [Journal]
  23. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and minimization techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:123-135 [Journal]

  24. Computational Analysis of .NET Remoting and Mobile agent in Distributed Environment [Citation Graph (, )][DBLP]


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