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Toshinori Sato: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu
    300MHz design methodology of VU for emotion synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:635-640 [Conf]
  2. Hidenori Sato, Toshinori Sato
    A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:830-833 [Conf]
  3. Asami Tanino, Toshinori Sato
    Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation. [Citation Graph (0, 0)][DBLP]
    CAINE, 2003, pp:282-287 [Conf]
  4. Toshinori Sato
    Exploiting Trivial Computation in Dependable Processors. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:168-173 [Conf]
  5. Toshinori Sato
    Exploiting Instruction Redundancy for Transient Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:547-554 [Conf]
  6. Toshinori Sato, Itsujiro Arita
    Simplifying Instruction Issue Logic in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:341-346 [Conf]
  7. Seiichiro Fujii, Toshinori Sato
    Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:217-226 [Conf]
  8. Toshinori Sato
    Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10285-10292 [Conf]
  9. Toshinori Sato
    A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1178-1185 [Conf]
  10. Toshinori Sato
    Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1281-1290 [Conf]
  11. Toshinori Sato, Itsujiro Arita
    Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:428-438 [Conf]
  12. Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita
    Influence of Compiler Optimizations on Value Prediction. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 2001, pp:312-321 [Conf]
  13. Masaharu Goto, Toshinori Sato
    Leakage Energy Reduction in Register Renaming. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2004, pp:890-895 [Conf]
  14. Toshinori Sato, Itsujiro Arita
    Partial Resolution in Data Value Predictors. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:69-76 [Conf]
  15. Toshinori Sato, Itsujiro Arita
    In Search of Efficient Reliable Processor Design. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:525-532 [Conf]
  16. Toshinori Sato, Itsujiro Arita
    Table size reduction for data value predictors by exploiting narrow width values. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:196-205 [Conf]
  17. Toshinori Sato
    Data Dependence Path Reductio with Tunneling Load Instructions. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:119-130 [Conf]
  18. Toshinori Sato
    Profile-Based Selection of Load Value and Address Predictors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1999, pp:17-28 [Conf]
  19. Toshinori Sato, Itsujiro Arita
    Low-Cost Value Predictors Using Frequent Value Locality. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:106-119 [Conf]
  20. Toshinori Sato, Itsujiro Arita
    Comprehensive Evaluation of an Instruction Reissue Mechanism. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2000, pp:78-87 [Conf]
  21. Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato
    Challenges in Evaluations for a Typical-Case Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:374-379 [Conf]
  22. Toshinori Sato, Yuji Kunitake
    A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:539-544 [Conf]
  23. Akihito Sakanaka, Toshinori Sato
    Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:530-539 [Conf]
  24. Toshinori Sato, Itsujiro Arita
    Reducing Energy Consumption via Low-Cost Value Prediction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:380-389 [Conf]
  25. Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu
    Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:553-562 [Conf]
  26. Takamasa Tokunaga, Toshinori Sato
    Profiling with Helper Threads. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:1-6 [Conf]
  27. Toshinori Sato, Itsujiro Arita
    The KIT COSMOS Processor: Introducing CONDOR. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  28. Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita
    The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1010-1016 [Conf]
  29. Toshinori Sato, Itsujiro Arita
    Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:225-232 [Conf]
  30. Toshinori Sato, Akihiro Chiyonobu
    Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. [Citation Graph (0, 0)][DBLP]
    PRDC, 2006, pp:369-370 [Conf]
  31. Yuu Tanaka, Toshinori Sato, Takenori Koushiro
    The potential in energy efficiency of a speculative chip-multiprocessor. [Citation Graph (0, 0)][DBLP]
    SPAA, 2004, pp:273-274 [Conf]
  32. Toshinori Sato, Kiichi Sugitani, Akihiko Hamano
    Evaluating Influence of Compiler Optimizations on Data Speculation. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2002, v:18, n:6, pp:1027-1036 [Journal]
  33. Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki
    Vector Unit Architecture for Emotion Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:2, pp:40-47 [Journal]
  34. Toshinori Sato, Itsujiro Arita
    Combining variable latency pipeline with instruction reuse for execution latency reduction. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2003, v:34, n:12, pp:11-21 [Journal]
  35. Takenori Koushiro, Toshinori Sato, Itsujiro Arita
    A trace-level value predictor for Contrail processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:3, pp:42-47 [Journal]
  36. Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
    A leakage-energy-reduction technique for highly-associative caches in embedded systems. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:50-54 [Journal]
  37. Toshinori Sato, Itsujiro Arita
    Tolerating Transient Faults through an Instruction Reissue Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:240-247 [Conf]
  38. Toshinori Sato, Yuji Kunitake
    Exploiting Input Variations for Energy Reduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:384-393 [Conf]
  39. Akihiro Chiyonobu, Toshinori Sato
    Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. [Citation Graph (0, 0)][DBLP]
    ISICT, 2004, pp:190-195 [Conf]
  40. Toshinori Sato
    Evaluating the impact of reissued instructions on data speculative processor performance. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:25, n:9-10, pp:469-482 [Journal]

  41. Indirect Tag Search Mechanism for Instruction Window Energy Reduction. [Citation Graph (, )][DBLP]

  42. Dependability, power, and performance trade-off on a multicore processor. [Citation Graph (, )][DBLP]

  43. Formulating MITF for a Multicore Processor with SEU Tolerance. [Citation Graph (, )][DBLP]

  44. Instruction Scheduling for Variation-Originated Variable Latencies. [Citation Graph (, )][DBLP]

  45. A case for exploiting complex arithmetic circuits towards performance yield enhancement. [Citation Graph (, )][DBLP]

  46. Uncriticality-directed scheduling for tackling variation and power challenges. [Citation Graph (, )][DBLP]

  47. Signal probability control for relieving NBTI in SRAM cells. [Citation Graph (, )][DBLP]

  48. Uncriticality-Directed Low-Power Instruction Scheduling. [Citation Graph (, )][DBLP]

  49. Power-Performance Trade-Off of a Dependable Multicore Processor. [Citation Graph (, )][DBLP]

  50. AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. [Citation Graph (, )][DBLP]

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