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Eugene Shragowitz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eric Q. Kang, Eugene Shragowitz
    Generic fuzzy logic CAD development tool. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Jung-Yong Lee, Eugene Shragowitz
    Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin
    Automated layout synthesis in the YASC silicon compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:447-453 [Conf]
  4. Rung-Bin Lin, Eugene Shragowitz
    Fuzzy Logic Approach to Placement Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:153-158 [Conf]
  5. Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
    Simulated annealing and combinatorial optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:293-299 [Conf]
  6. Suphachai Sutanthavibul, Eugene Shragowitz
    An Adaptive Timing-Driven Layout for High Speed VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:90-95 [Conf]
  7. Suphachai Sutanthavibul, Eugene Shragowitz
    Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:632-635 [Conf]
  8. Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
    An Analytical Approach to Floorplan Design and Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:187-192 [Conf]
  9. Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
    Experiments with simulated annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:748-752 [Conf]
  10. Jaebum Lee, Eugene Shragowitz, David Poli
    Bounds on net lengths for high-speed PCB. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:73-76 [Conf]
  11. Habib Youssef, Eugene Shragowitz
    Timing Constraints for Correct Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:24-27 [Conf]
  12. Jong Lee, Sartaj Sahni, Eugene Shragowitz
    A Hypecube Algorithm for the 0/1 Knapsack Problem. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:699-706 [Conf]
  13. Jun-Yong Lee, Eugene Shragowitz
    Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1219-1222 [Conf]
  14. H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul
    Net criticality revisited: an effective method to improve timing in physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:155-160 [Conf]
  15. Habib Youssef, Rung-Bin Lin, Eugene Shragowitz
    Bounds on Net Delays for Physical Design of Fast Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:111-118 [Conf]
  16. Habib Youssef, Eugene Shragowitz, Suphachai Sutanthavibul
    Prelayout timing analysis of cell-based VLSI designs. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:7, pp:367-379 [Journal]
  17. Jian Liu, Eugene Shragowitz, Wei-Tek Tsai
    Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic Design. [Citation Graph (0, 0)][DBLP]
    International Journal on Artificial Intelligence Tools, 2001, v:10, n:3, pp:303-323 [Journal]
  18. Eugene Shragowitz, Habib Youssef, Bing Lu
    Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like Models. [Citation Graph (0, 0)][DBLP]
    J. Comb. Optim., 2003, v:7, n:1, pp:5-22 [Journal]
  19. Jong Lee, Eugene Shragowitz, Sartaj Sahni
    A Hypercube Algorithm for the 0/1 Knapsack Problem. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1988, v:5, n:4, pp:438-456 [Journal]
  20. Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
    An adaptive timing-driven placement for high performance VLSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1488-1498 [Journal]
  21. Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
    An analytical approach to floorplan design and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:761-769 [Journal]
  22. Bing Lu, Jun Gu, Xiao-Dong Hu, Eugene Shragowitz
    Wire segmenting for buffer insertion based on RSTP-MSP. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2001, v:262, n:1, pp:257-267 [Journal]
  23. Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz
    Fuzzy logic approach to VLSI placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:489-501 [Journal]

  24. Iterative-Constructive Standard Cell Placer for High Speed and Low Power. [Citation Graph (, )][DBLP]

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