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Akira Matsuzawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa
    CMOS Image Sensors with Video Compression. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:595-600 [Conf]
  2. Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa
    A CMOS Smart Image Sensor LSI for Focal-Plane Compression. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:339-340 [Conf]
  3. Akira Matsuzawa
    How to make efficient communication, collaboration, and optimization from system to chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:417-418 [Conf]
  4. Akira Matsuzawa
    Driving the SoC developments for digital consumer electronics. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:5-7 [Conf]
  5. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
    A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:49-54 [Conf]
  6. Akira Matsuzawa
    High Quality Analog CMOS and Mixed Signal LSI Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:97-104 [Conf]
  7. Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa
    Design, Fabrications and Use of Mixed-Signal IC Testability Structures. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:489-498 [Conf]
  8. Dwi Handoko, Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa
    Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:12, pp:1084-0 [Journal]
  9. Win Chaivipas, Akira Matsuzawa, Philipus Chandra Oh
    Feedforward compensation technique for all digital phase locked loop based synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  10. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
    A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:377-387 [Journal]

  11. A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. [Citation Graph (, )][DBLP]


  12. Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. [Citation Graph (, )][DBLP]


  13. "The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. [Citation Graph (, )][DBLP]


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