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Youngsoo Shin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha
    An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Hyung-Ock Kim, Youngsoo Shin
    Analysis and optimization of gate leakage current of power gating circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:565-569 [Conf]
  3. Youngsoo Shin, Kiyoung Choi
    Narrow bus encoding for low power systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:217-220 [Conf]
  4. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  5. Youngsoo Shin, Kiyoung Choi
    Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:3-8 [Conf]
  6. Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo
    Physical design methodology of power gating circuits for standard-cell-based design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:109-112 [Conf]
  7. Youngsoo Shin, Kiyoung Choi
    Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:134-139 [Conf]
  8. Youngsoo Shin, Daehong Kim, Kiyoung Choi
    Schedulability-driven performance analysis of multiple mode embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:495-500 [Conf]
  9. Youngsoo Shin, Takayasu Sakurai
    Coupling-Driven Bus Design for Low-Power Application-Specific Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:750-753 [Conf]
  10. Youngsoo Shin, Kiyoung Choi
    Rate Assignment for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10237-0 [Conf]
  11. Youngsoo Shin, Kiyoung Choi
    Software synthesis through task decomposition by dependency analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:98-104 [Conf]
  12. Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
    Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:365-368 [Conf]
  13. Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jaehee Won, Kiyoung Choi
    Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:924-927 [Conf]
  14. Youngsoo Shin, Hyung-Ock Kim
    Analysis of power consumption in VLSI global interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4713-4716 [Conf]
  15. Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
    Architecting voltage islands in core-based system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:180-185 [Conf]
  16. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of system level bus. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:127-129 [Conf]
  17. Youngsoo Shin, Takayasu Sakurai
    Estimation of power distribution in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:370-375 [Conf]
  18. Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin
    A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:482-487 [Conf]
  19. Youngsoo Shin, Hyung-Ock Kim
    Cell-Based Semicustom Design of Zigzag Power Gating Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:527-532 [Conf]
  20. Byunghee Choi, Youngsoo Shin
    Lookup Table-Based Adaptive Body Biasing of Multiple Macros. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:533-538 [Conf]
  21. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  22. Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai
    /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2005, v:7, n:1, pp:67-74 [Journal]
  23. Jun Seomun, Jaehyun Kim, Youngsoo Shin
    Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:103-106 [Conf]
  24. Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, J. Y. Choi
    Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:758-766 [Journal]
  25. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of application-specific systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:377-383 [Journal]
  26. Youngsoo Shin, Kiyoung Choi, Young-hoon Chang
    Narrow bus encoding for low-power DSP systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:656-660 [Journal]

  27. Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. [Citation Graph (, )][DBLP]


  28. Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. [Citation Graph (, )][DBLP]


  29. Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. [Citation Graph (, )][DBLP]


  30. Register allocation for high-level synthesis using dual supply voltages. [Citation Graph (, )][DBLP]


  31. Synthesis and implementation of active mode power gating circuits. [Citation Graph (, )][DBLP]


  32. Pulsed-latch aware placement for timing-integrity optimization. [Citation Graph (, )][DBLP]


  33. HLS-l: High-level synthesis of high performance latch-based circuits. [Citation Graph (, )][DBLP]


  34. Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. [Citation Graph (, )][DBLP]


  35. Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. [Citation Graph (, )][DBLP]


  36. Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. [Citation Graph (, )][DBLP]


  37. Power-aware slack distribution for hierarchical VLSI design. [Citation Graph (, )][DBLP]


  38. 3-D thermal simulation with dynamic power profiles. [Citation Graph (, )][DBLP]


  39. Power-gating-aware high-level synthesis. [Citation Graph (, )][DBLP]


  40. Frequency and yield optimization using power gates in power-constrained designs. [Citation Graph (, )][DBLP]


  41. Wakeup synthesis and its buffered tree construction for power gating circuit designs. [Citation Graph (, )][DBLP]


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