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Hyunchul Shin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wonjong Kim, Hyunchul Shin
    Hierarchical LVS Based on Hierarchy Rebuilding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:379-384 [Conf]
  2. Chunghee Kim, Hyunchul Shin, Young-Uk Yu
    Performance-driven circuit partitioning for prototyping by using multiple FPGA chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Wonjong Kim, Joohack Lee, Hyunchul Shin
    A New Hierarchical Layout Compactor Using Simplified Graph Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:323-326 [Conf]
  4. Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin
    Two-dimensional compaction by ``zone refining''. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:115-122 [Conf]
  5. Hyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung
    A combined hierarchical placement algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:164-169 [Conf]
  6. Inho Lee, Joung-Youn Kim, Yeon-Ho Im, Yunseok Choi, Hyunchul Shin, Changyoung Han, Donghyun Kim, Hyoungjoon Park, Young-Il Seo, Kyusik Chung, Chang-Hyo Yu, Kanghyup Chun, Lee-Sup Kim
    A hardware-like high-level language based environment for 3D graphics architecture exploration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:512-515 [Conf]
  7. Chunghee Kim, Hyunchul Shin
    A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:560-568 [Journal]
  8. Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli
    A Detailed Router Based on Incremental Routing Modifications: Mighty. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:942-955 [Journal]
  9. Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin
    'Zone-refining' techniques for IC layout compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:167-179 [Journal]
  10. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
    A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:254-267 [Journal]
  11. Hyunchul Shin, Chunghee Kim
    A simple yet effective technique for partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:380-386 [Journal]
  12. Hyunchul Shin, Chunghee Kim
    Performance-oriented technology mapping for LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:323-327 [Journal]
  13. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
    A hardware cost minimized fast Phong shader. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:297-304 [Journal]

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