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Yong Chang Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:592-597 [Conf]
  2. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:300-0 [Conf]
  3. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational test generation for various classes of acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1078-1087 [Conf]
  4. Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
    Exclusive Test and its Applications to Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:143-148 [Conf]
  5. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:592-597 [Conf]
  6. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:143-148 [Conf]
  7. Yong Chang Kim, Kewal K. Saluja
    Sequential test generators: past, present and future. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:41-54 [Journal]
  8. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational automatic test pattern generation for acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:948-956 [Journal]

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