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Junhyung Um: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Taewhan Kim, Junhyung Um
    A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:313-316 [Conf]
  2. Junhyung Um, Taewhan Kim
    Layout-aware synthesis of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:207-212 [Conf]
  3. Junhyung Um, Taewhan Kim, C. L. Liu
    A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:98-103 [Conf]
  4. Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim
    A systematic IP and bus subsystem modeling for platform-based system design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:560-564 [Conf]
  5. Junhyung Um, Taewhan Kim
    Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:197-200 [Conf]
  6. Junhyung Um, Jae-Hoon Kim, Taewhan Kim
    Layout-driven resource sharing in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:614-618 [Conf]
  7. Junhyung Um, Taewhan Kim, C. L. Liu
    Optimal allocation of carry-save-adders in arithmetic optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:410-413 [Conf]
  8. Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Thewhan KimU
    An efficient inverse multiplier/divider architecture for cryptography systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:149-152 [Conf]
  9. Junhyung Um, Taewhan Kim
    An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:215-233 [Journal]
  10. Taewhan Kim, Junhyung Um
    A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:615-624 [Journal]
  11. Junhyung Um, Taewhan Kim
    Synthesis of arithmetic circuits considering layout effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1487-1503 [Journal]
  12. Junhyung Um, Taewhan Kim
    Resource Sharing Combined with Layout Effects in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:231-243 [Journal]

  13. In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. [Citation Graph (, )][DBLP]

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