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Kimiyoshi Usami:
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Publications of Author
- Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi
A Clock-Gating Method for Low-Power LSI Design. [Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:307-312 [Conf]
- Naoaki Ohkubo, Kimiyoshi Usami
Delay modeling and static timing analysis for MTCMOS circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:570-575 [Conf]
- Kimiyoshi Usami, Mutsunori Igarashi
Low-power design methodology and applications utilizing dual supply voltages. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:123-128 [Conf]
- Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori
Datapath Generator Based on Gate-Level Symbolic Layout. [Citation Graph (0, 0)][DBLP] DAC, 1990, pp:388-393 [Conf]
- Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Function-level power estimation methodology for microprocessors. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:810-813 [Conf]
- Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. [Citation Graph (0, 0)][DBLP] DAC, 1998, pp:483-488 [Conf]
- Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka
A low-power design method using multiple supply voltages. [Citation Graph (0, 0)][DBLP] ISLPED, 1997, pp:36-41 [Conf]
- Kimiyoshi Usami, Mark Horowitz
Clustered voltage scaling technique for low-power design. [Citation Graph (0, 0)][DBLP] ISLPD, 1995, pp:3-8 [Conf]
- Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
Automated selective multi-threshold design for ultra-low standby applications. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:202-206 [Conf]
- Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Code Coverage-Based Power Estimation Techniques for Microprocessors. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:557-0 [Journal]
Cache Controller Design on Ultra Low Leakage Embedded Processors. [Citation Graph (, )][DBLP]
Overview on Low Power SoC Design Technology. [Citation Graph (, )][DBLP]
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. [Citation Graph (, )][DBLP]
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. [Citation Graph (, )][DBLP]
A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]
Adaptive power gating for function units in a microprocessor. [Citation Graph (, )][DBLP]
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. [Citation Graph (, )][DBLP]
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