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Junji Kitamichi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Junji Kitamichi, Hiroyuki Kageyama, Nobuo Funabiki
    Formal Verification Method for Combinatorial Circuits at High Level Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:319-0 [Conf]
  2. Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi
    Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:177-180 [Conf]
  3. Atsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino, Ana R. Cavalli
    A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs. [Citation Graph (0, 0)][DBLP]
    ICOIN, 2001, pp:155-162 [Conf]
  4. Toshiyuki Ito, Junji Kitamichi, Kenichi Kuroda, Yuichi Okuyama
    A Master-Slave Adaptive Load-Distribution Processor Model on PCA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  5. Teruo Higashino, Keiichi Yasumoto, Junji Kitamichi, Kenichi Taniguchi
    Hardware synthesis from a restricted class of LOTOS expressions. [Citation Graph (0, 0)][DBLP]
    PSTV, 1994, pp:379-386 [Conf]
  6. Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi
    Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:165-184 [Conf]
  7. Kenji Asano, Junji Kitamichi, Kenichi Kuroda
    Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:373-378 [Conf]
  8. Nobuo Funabiki, Junji Kitamichi, Seishi Nishikawa
    An evolutionary neural network approach for module orientation problems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 1998, v:28, n:6, pp:849-855 [Journal]
  9. Nobuo Funabiki, M. Yoda, Junji Kitamichi, Seishi Nishikawa
    A gradual neural network approach for FPGA segmented channel routing problems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 1999, v:29, n:4, pp:481-489 [Journal]

  10. A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem. [Citation Graph (, )][DBLP]


  11. A Modeling of a Dynamically Reconfigurable Processor Using SystemC. [Citation Graph (, )][DBLP]


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