The SCEAS System
Navigation Menu

Search the dblp DataBase


Qiang Xu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ho Fai Ko, Qiang Xu, Nicola Nicolici
    Register-transfer level functional scan for hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1172-1175 [Conf]
  2. Qiang Xu, Nicola Nicolici
    Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:2-7 [Conf]
  3. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
    Multi-frequency wrapper design and optimization for embedded cores under average power constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:123-128 [Conf]
  4. Qiang Xu, Nicola Nicolici
    Delay Fault Testing of Core-Based Systems-on-a-Chi. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10744-10752 [Conf]
  5. Qiang Xu, Nicola Nicolici
    Wrapper Design for Testing IP Cores with Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:416-421 [Conf]
  6. Qiang Xu
    Content Management and Resources Integration: A Practice in Shanghai Digital Library. [Citation Graph (0, 0)][DBLP]
    ICADL, 2004, pp:25-34 [Conf]
  7. Bai Hong Fang, Qiang Xu, Nicola Nicolici
    Hardware/Software Co-testing of Embedded Memories in Complex SOCs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:599-606 [Conf]
  8. Qiang Xu, Nicola Nicolici
    On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:622-631 [Conf]
  9. Qiang Xu, Nicola Nicolici
    Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1196-1202 [Conf]
  10. Qiang Xu, Nicola Nicolici
    DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:470-485 [Journal]
  11. Qiang Xu, Nicola Nicolici
    Modular SOC testing with reduced wrapper count. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1894-1908 [Journal]
  12. Qiang Xu, Nicola Nicolici
    Multifrequency TAM design for hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:181-196 [Journal]
  13. Qiang Xu, Nicola Nicolici
    Wrapper design for multifrequency IP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:678-685 [Journal]
  14. Qiang Xu, Nicola Nicolici
    Modular and rapid testing of SOCs with unwrapped logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1275-1285 [Journal]
  15. Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
    SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:676-681 [Conf]
  16. Shan Tang, Qiang Xu
    A multi-core debug platform for NoC-based systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:870-875 [Conf]
  17. Qiang Xu, Jaspal Subhlok
    Automatic clustering of grid nodes. [Citation Graph (0, 0)][DBLP]
    GRID, 2005, pp:227-233 [Conf]
  18. Qiang Xu, Baosheng Wang, F. Y. Young
    Retention-Aware Test Scheduling for BISTed Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:83-88 [Conf]
  19. Xiucheng Dong, Haibin Wang, Qiang Xu, Xiaoxiao Zhao
    Research on Applications of a New-Type Fuzzy-Neural Network Controller. [Citation Graph (0, 0)][DBLP]
    LSMS (1), 2007, pp:679-687 [Conf]

  20. A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems. [Citation Graph (, )][DBLP]

  21. On reducing both shift and capture power for scan-based testing. [Citation Graph (, )][DBLP]

  22. Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks. [Citation Graph (, )][DBLP]

  23. On reliable modular testing with vulnerable test access mechanisms. [Citation Graph (, )][DBLP]

  24. Interconnection fabric design for tracing signals in post-silicon validation. [Citation Graph (, )][DBLP]

  25. On systematic illegal state identification for pseudo-functional testing. [Citation Graph (, )][DBLP]

  26. Performance yield-driven task allocation and scheduling for MPSoCs under process variation. [Citation Graph (, )][DBLP]

  27. In-band Cross-Trigger Event Transmission for Transaction-Based Debug. [Citation Graph (, )][DBLP]

  28. Re-Examining the Use of Network-on-Chip as Test Access Mechanism. [Citation Graph (, )][DBLP]

  29. Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. [Citation Graph (, )][DBLP]

  30. iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. [Citation Graph (, )][DBLP]

  31. Trace signal selection for visibility enhancement in post-silicon validation. [Citation Graph (, )][DBLP]

  32. Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. [Citation Graph (, )][DBLP]

  33. A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment. [Citation Graph (, )][DBLP]

  34. Test architecture design and optimization for three-dimensional SoCs. [Citation Graph (, )][DBLP]

  35. AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs. [Citation Graph (, )][DBLP]

  36. Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. [Citation Graph (, )][DBLP]

  37. Layout-aware pseudo-functional testing for critical paths considering power supply noise effects. [Citation Graph (, )][DBLP]

  38. Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. [Citation Graph (, )][DBLP]

  39. The Improved Fuzzy Classification Model on Disaster Loss. [Citation Graph (, )][DBLP]

  40. Fuzzy Reliability Analysis of Deep Sliding Plane in Rock Foundation under Dam. [Citation Graph (, )][DBLP]

  41. Construction and Evaluation of Coordinated Performance Skeletons. [Citation Graph (, )][DBLP]

  42. On capture power-aware test data compression for scan-based testing. [Citation Graph (, )][DBLP]

  43. Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. [Citation Graph (, )][DBLP]

  44. Automatic construction of coordinated performance skeletons. [Citation Graph (, )][DBLP]

  45. Efficient Discovery of Loop Nests in Execution Traces. [Citation Graph (, )][DBLP]

  46. Anatomizing application performance differences on smartphones. [Citation Graph (, )][DBLP]

  47. On Modeling the Lifetime Reliability of Homogeneous Manycore Systems. [Citation Graph (, )][DBLP]

  48. Logicalization of communication traces from parallel execution. [Citation Graph (, )][DBLP]

  49. Performance prediction with skeletons. [Citation Graph (, )][DBLP]

Search in 0.828secs, Finished in 0.831secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002