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Nicola Nicolici: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ho Fai Ko, Qiang Xu, Nicola Nicolici
    Register-transfer level functional scan for hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1172-1175 [Conf]
  2. Ho Fai Ko, Nicola Nicolici
    Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:454-459 [Conf]
  3. Qiang Xu, Nicola Nicolici
    Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:2-7 [Conf]
  4. Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
    Multi-frequency wrapper design and optimization for embedded cores under average power constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:123-128 [Conf]
  5. Qiang Xu, Nicola Nicolici
    Delay Fault Testing of Core-Based Systems-on-a-Chi. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10744-10752 [Conf]
  6. Qiang Xu, Nicola Nicolici
    Wrapper Design for Testing IP Cores with Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:416-421 [Conf]
  7. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:604-611 [Conf]
  8. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Test Data Compression: The System Integrator's Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10726-10731 [Conf]
  9. Nicola Nicolici, Bashir M. Al-Hashimi
    Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:715-722 [Conf]
  10. Nicola Nicolici, Bashir M. Al-Hashimi
    Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:802- [Conf]
  11. Nicola Nicolici, Bashir M. Al-Hashimi
    Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:289-0 [Conf]
  12. Bai Hong Fang, Nicola Nicolici
    Power-Constrained Embedded Memory BIST Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:451-458 [Conf]
  13. Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici
    Embedded Compact Deterministic Test for IP-Protected Cores. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:519-0 [Conf]
  14. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan Architecture for Shift and Capture Cycle Power Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:129-137 [Conf]
  15. Bai Hong Fang, Qiang Xu, Nicola Nicolici
    Hardware/Software Co-testing of Embedded Memories in Complex SOCs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:599-606 [Conf]
  16. Ho Fai Ko, Nicola Nicolici
    Functional Illinois Scan Design at RTL. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:78-81 [Conf]
  17. Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici
    Compressed Embedded Diagnosis of Logic Cores. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:534-539 [Conf]
  18. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:474-479 [Conf]
  19. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power constrained test scheduling using power profile manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:251-254 [Conf]
  20. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:64-73 [Conf]
  21. Nicola Nicolici, Bashir M. Al-Hashimi
    Power conscious test synthesis and scheduling for BIST RTL data paths. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:662-671 [Conf]
  22. Nicola Nicolici, Bashir M. Al-Hashimi
    Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:72-81 [Conf]
  23. Qiang Xu, Nicola Nicolici
    On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:622-631 [Conf]
  24. Qiang Xu, Nicola Nicolici
    Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1196-1202 [Conf]
  25. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:423-432 [Conf]
  26. Nicola Nicolici, Bashir M. Al-Hashimi
    Power-Conscious Test Synthesis and Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:48-55 [Journal]
  27. Nicola Nicolici, Bashir M. Al-Hashimi
    Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:6, pp:721-734 [Journal]
  28. Nicola Nicolici, Bashir M. Al-Hashimi
    Correction to the Proof of Theorem 2 in ``Parallel Signature Analysis Design with Bounds on Aliasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1426- [Journal]
  29. Qiang Xu, Nicola Nicolici
    DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:470-485 [Journal]
  30. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Variable-length input Huffman coding for system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:783-796 [Journal]
  31. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Addressing useless test data in core-based system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1568-1580 [Journal]
  32. Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams
    BIST hardware synthesis for RTL data paths based on testcompatibility classes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1375-1385 [Journal]
  33. Qiang Xu, Nicola Nicolici
    Modular SOC testing with reduced wrapper count. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1894-1908 [Journal]
  34. Qiang Xu, Nicola Nicolici
    Multifrequency TAM design for hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:181-196 [Journal]
  35. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power profile manipulation: a new approach for reducing test application time under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1217-1225 [Journal]
  36. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1142-1153 [Journal]
  37. Qiang Xu, Nicola Nicolici
    Wrapper design for multifrequency IP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:678-685 [Journal]
  38. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Synchronization overhead in SOC compressed test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:140-152 [Journal]
  39. Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici
    Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:537-548 [Journal]
  40. Qiang Xu, Nicola Nicolici
    Modular and rapid testing of SOCs with unwrapped logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1275-1285 [Journal]
  41. Ehab Anis, Nicola Nicolici
    Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:225-230 [Conf]
  42. Nicola Nicolici, Xiaoqing Wen
    Embedded Tutorial on Low Power Test. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:202-210 [Conf]

  43. A novel optimal single constant multiplication algorithm. [Citation Graph (, )][DBLP]


  44. Embedded memory binding in FPGAs. [Citation Graph (, )][DBLP]


  45. Post-silicon validation opportunities, challenges and recent advances. [Citation Graph (, )][DBLP]


  46. Robust design methods for hardware accelerators for iterative algorithms in scientific computing. [Citation Graph (, )][DBLP]


  47. Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. [Citation Graph (, )][DBLP]


  48. Power-Aware Testing and Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  49. On Automated Trigger Event Generation in Post-Silicon Validation. [Citation Graph (, )][DBLP]


  50. Finite Precision bit-width allocation using SAT-Modulo Theory. [Citation Graph (, )][DBLP]


  51. Automated data analysis solutions to silicon debug. [Citation Graph (, )][DBLP]


  52. Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. [Citation Graph (, )][DBLP]


  53. RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. [Citation Graph (, )][DBLP]


  54. A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. [Citation Graph (, )][DBLP]


  55. Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. [Citation Graph (, )][DBLP]


  56. Automated silicon debug data analysis techniques for a hardware data acquisition environment. [Citation Graph (, )][DBLP]


  57. Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. [Citation Graph (, )][DBLP]


  58. Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. [Citation Graph (, )][DBLP]


  59. Hardware-based parallel computing for real-time haptic rendering of deformable objects. [Citation Graph (, )][DBLP]


  60. DATE 07 workshop on diagnostic services in NoCs. [Citation Graph (, )][DBLP]


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