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Sharad Malik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Noriya Kobayashi, Sharad Malik
    Delay abstraction in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Janett Mohnke, Paul Molitor, Sharad Malik
    Limits of using signatures for permutation independent Boolean comparison. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Yinlei Yu, Sharad Malik
    Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1047-1051 [Conf]
  4. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:228-239 [Conf]
  5. Lintao Zhang, Sharad Malik
    The Quest for Efficient Boolean Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
    CADE, 2002, pp:295-313 [Conf]
  6. Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik
    Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:157-164 [Conf]
  7. Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip
    Symmetry Reduction in SAT-Based Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2005, pp:125-138 [Conf]
  8. Lintao Zhang, Sharad Malik
    The Quest for Efficient Boolean Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:17-36 [Conf]
  9. Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
    Optimal Live Range Merge for Address Register Allocation in Embedded Programs. [Citation Graph (0, 0)][DBLP]
    CC, 2001, pp:274-288 [Conf]
  10. Aarti Gupta, Pranav Ashar, Sharad Malik
    Exploiting Retiming in a Guided Simulation Based Validation Methodology. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:350-353 [Conf]
  11. Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
    Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:2-6 [Conf]
  12. Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August
    Facilitating reuse in hardware models with enhanced type inference. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:86-91 [Conf]
  13. Shaojie Wang, Sharad Malik
    Synthesizing operating system based device drivers in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:37-44 [Conf]
  14. Fen Xie, Margaret Martonosi, Sharad Malik
    Efficient behavior-driven runtime dynamic voltage scaling policies. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:105-110 [Conf]
  15. Xinping Zhu, Wei Qin, Sharad Malik
    Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:66-71 [Conf]
  16. Lintao Zhang, Sharad Malik
    Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation. [Citation Graph (0, 0)][DBLP]
    CP, 2002, pp:200-215 [Conf]
  17. Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
    Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:591-596 [Conf]
  18. Pranav Ashar, Sharad Malik
    Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:77-80 [Conf]
  19. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:359-365 [Conf]
  20. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified Timing Verification and the Transition Delay of a Logic Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:549-555 [Conf]
  21. Srinivas Devadas, Sharad Malik
    A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:242-247 [Conf]
  22. Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
    Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:747-750 [Conf]
  23. Aarti Gupta, Sharad Malik, Pranav Ashar
    Toward Formalizing a Validation Methodology Using Simulation Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:740-745 [Conf]
  24. Zhining Huang, Sharad Malik
    Exploiting operation level parallelism through dynamically reconfigurable datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:337-342 [Conf]
  25. Horng-Fei Jyu, Sharad Malik
    Statistical Delay Modeling in Logic Design and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:126-130 [Conf]
  26. Yau-Tsun Steven Li, Sharad Malik
    Performance Analysis of Embedded Software Using Implicit Path Enumeration. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:456-461 [Conf]
  27. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is Redundancy Necessary to Reduce Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:228-234 [Conf]
  28. Sharad Malik, D. K. Arvind, Edward Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf
    Embedded systems education (panel abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:519- [Conf]
  29. Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li
    Static Timing Analysis of Embedded Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:147-152 [Conf]
  30. Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik
    Chaff: Engineering an Efficient SAT Solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:530-535 [Conf]
  31. Wei Qin, Sharad Malik
    Automated synthesis of efficient binary decoders for retargetable software toolkits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:764-769 [Conf]
  32. Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
    Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:667-672 [Conf]
  33. Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey
    Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:479- [Conf]
  34. Vivek Tiwari, Pranav Ashar, Sharad Malik
    Technology Mapping for Lower Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:74-79 [Conf]
  35. Ying Zhao, Sharad Malik
    Exact Memory Size Estimation for Array Computations without Loop Unrolling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:811-816 [Conf]
  36. Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
    Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:194-199 [Conf]
  37. Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang
    Challenges in code generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:48-64 [Conf]
  38. Zhaohui Fu, Yinlei Yu, Sharad Malik
    Considering Circuit Observability Don't Cares in CNF Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1108-1113 [Conf]
  39. Zhining Huang, Sharad Malik
    Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:735- [Conf]
  40. Wei Qin, Sharad Malik
    Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10556-10561 [Conf]
  41. Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
    Modeling and Integration of Peripheral Devices in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10136-10141 [Conf]
  42. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1238-1243 [Conf]
  43. Lintao Zhang, Sharad Malik
    Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10880-10885 [Conf]
  44. Xinping Zhu, Sharad Malik
    Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1244-1249 [Conf]
  45. Sharad Malik
    Embedded Software Implementation Tools for Fully Programmable Application Specific Systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:254-256 [Conf]
  46. Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh
    Design Tools for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:319-333 [Conf]
  47. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
    Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1308-1315 [Conf]
  48. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Accelerating Boolean Satisfiability with Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:186-195 [Conf]
  49. Cameron Brien, Sharad Malik
    Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:49-50 [Conf]
  50. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Solving Boolean Satisfiability with Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:326-335 [Conf]
  51. Sharad Malik
    A Case for Runtime Validation of Hardware. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2005, pp:30-42 [Conf]
  52. Ali Alphan Bayazit, Sharad Malik
    Complementary use of runtime validation and model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1052-1059 [Conf]
  53. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multi-cycle false paths in the performance optimization of sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:510-517 [Conf]
  54. Pranav Ashar, Aarti Gupta, Sharad Malik
    Using complete-1-distinguishability for FSM equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:346-353 [Conf]
  55. Pranav Ashar, Sharad Malik
    Fast functional simulation using branching programs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:408-412 [Conf]
  56. Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
    Incremental CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:236-243 [Conf]
  57. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Delay Computation in Combinational Logic Circuits: Theory and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:176-179 [Conf]
  58. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Verification of asynchronous interface circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:188-195 [Conf]
  59. Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
    Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:286-292 [Conf]
  60. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
    Performance estimation of embedded software with instruction cache modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:380-387 [Conf]
  61. Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:560-563 [Conf]
  62. Sharad Malik
    Analysis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:618-625 [Conf]
  63. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Optimization of Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:410-413 [Conf]
  64. Vigyan Singhal, Sharad Malik, Robert K. Brayton
    The case for retiming with explicit reset circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:618-625 [Conf]
  65. Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
    Algorithms for Discrete Function Manipulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:92-95 [Conf]
  66. Ashok Sudarsanam, Sharad Malik
    Memory bank and register allocation in software synthesis for ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:388-392 [Conf]
  67. Vivek Tiwari, Sharad Malik, Andrew Wolfe
    Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:384-390 [Conf]
  68. Zhaohui Fu, Sharad Malik
    Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:852-859 [Conf]
  69. Lintao Zhang, Sharad Malik
    Conflict driven learning in a quantified Boolean Satisfiability solver. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:442-449 [Conf]
  70. Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik
    Efficient Conflict Driven Learning in Boolean Satisfiability Solver. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:279-285 [Conf]
  71. Xinping Zhu, Sharad Malik
    A hierarchical modeling framework for on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:663-671 [Conf]
  72. Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik
    Statistical Timing Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:38-43 [Conf]
  73. Horng-Fei Jyu, Sharad Malik
    Statistical Timing Optimization of Combinatorial Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:77-80 [Conf]
  74. Kurt Keutzer, Sharad Malik, A. Richard Newton
    From ASIC to ASIP: The Next Design Discontinuity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:84-90 [Conf]
  75. Ying Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan
    Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:447-452 [Conf]
  76. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Automated cache optimizations using CME driven diagnosis. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:316-326 [Conf]
  77. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Cache Miss Equations: An Analytical Representation of Cache Misses. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:317-324 [Conf]
  78. David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai
    Achieving Structural and Composable Modeling of Complex Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004, pp:- [Conf]
  79. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:221-226 [Conf]
  80. Fen Xie, Margaret Martonosi, Sharad Malik
    Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:287-292 [Conf]
  81. Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano
    Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:38-43 [Conf]
  82. Guido Araujo, Ashok Sudarsanam, Sharad Malik
    Instruction Set Design and Optimizations for Address Computation in DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:102-107 [Conf]
  83. Kaiyu Chen, Sharad Malik, David I. August
    Retargetable static timing analysis for embedded software. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:39-44 [Conf]
  84. Guido Araujo, Sharad Malik
    Optimal code generation for embedded memory non-homogeneous register architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:36-41 [Conf]
  85. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and low-power scheduling techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:110-115 [Conf]
  86. Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan
    Accelerating boolean satisfiability through application specific processing. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:244-249 [Conf]
  87. Yau-Tsun Steven Li, Sharad Malik
    Performance Analysis of Embedded Software Using Implicit Path Enumeration. [Citation Graph (0, 0)][DBLP]
    Workshop on Languages, Compilers, & Tools for Real-Time Systems, 1995, pp:88-98 [Conf]
  88. Wei Qin, Subramanian Rajagopalan, Sharad Malik
    A formal concurrency model based architecture description language for synthesis of software development tools. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:47-56 [Conf]
  89. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    Power-driven Design of Router Microarchitectures in On-chip Networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:105-116 [Conf]
  90. Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik
    Orion: a power-performance simulator for interconnection networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:294-305 [Conf]
  91. Wei Qin, Sharad Malik
    A Study of Architecture Description Languages from a Model-based Perspective. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:3-11 [Conf]
  92. Fen Xie, Margaret Martonosi, Sharad Malik
    Compile-time dynamic voltage scaling settings: opportunities and limits. [Citation Graph (0, 0)][DBLP]
    PLDI, 2003, pp:49-62 [Conf]
  93. Kaiyu Chen, Sharad Malik
    Dependable Multithreaded Processing Using Runtime Validation. [Citation Graph (0, 0)][DBLP]
    PRDC, 2006, pp:275-286 [Conf]
  94. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
    Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1995, pp:298-307 [Conf]
  95. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
    Cache modeling for real-time software: beyond direct mapped instruction caches. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1996, pp:254-263 [Conf]
  96. Yogesh S. Mahajan, Zhaohui Fu, Sharad Malik
    Zchaff2004: An Efficient SAT Solver. [Citation Graph (0, 0)][DBLP]
    SAT (Selected Papers, 2004, pp:360-375 [Conf]
  97. Zhaohui Fu, Sharad Malik
    On Solving the Partial MAX-SAT Problem. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:252-265 [Conf]
  98. Yinlei Yu, Sharad Malik
    Lemma Learning in SMT on Linear Constraints. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:142-155 [Conf]
  99. Darsh P. Ranjan, Daijue Tang, Sharad Malik
    A Comparative Study of 2QBF Algorithms. [Citation Graph (0, 0)][DBLP]
    SAT, 2004, pp:- [Conf]
  100. Daijue Tang, Sharad Malik
    Solving Quantified Boolean Formulas with Circuit Observability Don't Cares. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:368-381 [Conf]
  101. Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik
    Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. [Citation Graph (0, 0)][DBLP]
    SAT, 2004, pp:- [Conf]
  102. Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik
    Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. [Citation Graph (0, 0)][DBLP]
    SAT (Selected Papers, 2004, pp:292-305 [Conf]
  103. Lintao Zhang, Sharad Malik
    Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms. [Citation Graph (0, 0)][DBLP]
    SAT, 2003, pp:287-298 [Conf]
  104. Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno
    CAD Techniques for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:608- [Conf]
  105. T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
    Processor Evaluation in an Embedded Systems Design Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:98-103 [Conf]
  106. Kurt Keutzer, Sharad Malik
    Register Transfer Level Synthesis: From Theory to Practice. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:2- [Conf]
  107. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:104-109 [Conf]
  108. Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
    Instruction Level Power Analysis and Optimization of Software. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:326-328 [Conf]
  109. Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez
    Dynamic Power Management for Microprocessors: A Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:185-192 [Conf]
  110. Zhaohui Fu, Sharad Malik
    Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:37-42 [Conf]
  111. N. Nandhakumar, Sharad Malik
    Multisensor Integration for Underwater Scene Classification. [Citation Graph (0, 0)][DBLP]
    Appl. Intell., 1995, v:5, n:3, pp:207-216 [Journal]
  112. Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik
    Developing Architectural Platforms: A Disciplined Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:6-16 [Journal]
  113. Carl Pixley, Sharad Malik
    Guest Editors' Introduction: Exploring Synergies for Design Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:461-463 [Journal]
  114. Janett Mohnke, Paul Molitor, Sharad Malik
    Limits of Using Signatures for Permutation Independent Boolean Comparison. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:2, pp:167-191 [Journal]
  115. David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann
    Achieving Structural and Composable Modeling of Complex Systems. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:2-3, pp:81-101 [Journal]
  116. Janett Mohnke, Paul Molitor, Sharad Malik
    Establishing latch correspondence for sequential circuits using distinguishing signatures. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:33-46 [Journal]
  117. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:1, pp:26-35 [Journal]
  118. Janett Mohnke, Paul Molitor, Sharad Malik
    Application of BDDs in Boolean matching techniques for formal logic combinational verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:2, pp:207-216 [Journal]
  119. Fen Xie, Margaret Martonosi, Sharad Malik
    Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:3, pp:323-367 [Journal]
  120. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multicycle false paths in the performance optimization of sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1067-1075 [Journal]
  121. Pranav Ashar, Sharad Malik
    Functional timing analysis using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1025-1030 [Journal]
  122. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Computation of floating mode delay in combinational circuits: theory and algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1913-1923 [Journal]
  123. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Computation of floating mode delay in combinational circuits: practice and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1924-1936 [Journal]
  124. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:814-822 [Journal]
  125. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is redundancy necessary to reduce delay? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:427-435 [Journal]
  126. Noriya Kobayashi, Sharad Malik
    Delay abstraction in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1205-1212 [Journal]
  127. Yau-Tsun Steven Li, Sharad Malik
    Performance analysis of embedded software using implicit path enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1477-1487 [Journal]
  128. Sharad Malik
    Analysis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:950-956 [Journal]
  129. Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Symbolic minimization of multilevel logic and the input encoding problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:825-843 [Journal]
  130. Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Retiming and resynthesis: optimizing sequential networks with combinational techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:74-84 [Journal]
  131. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:568-578 [Journal]
  132. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1408-1414 [Journal]
  133. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
    A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]
  134. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1051-1060 [Journal]
  135. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Using configurable computing to accelerate Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:861-868 [Journal]
  136. Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo
    The design of dynamically reconfigurable datapath coprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:361-384 [Journal]
  137. Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August
    The Liberty Simulation Environment: A deliberate approach to high-level system modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2006, v:24, n:3, pp:211-249 [Journal]
  138. Guido Araujo, Sharad Malik
    Code generation for fixed-point DSPs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:136-161 [Journal]
  139. Pranav Ashar, Aarti Gupta, Sharad Malik
    Using complete-1-distinguishability for FSM equivalence checking. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:569-590 [Journal]
  140. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
    Performance estimation of embedded software with instruction cache modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:3, pp:257-279 [Journal]
  141. Ashok Sudarsanam, Sharad Malik
    Simultaneous reference allocation in code generation for dual data memory bank ASIPs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:242-264 [Journal]
  142. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Cache miss equations: a compiler framework for analyzing and tuning memory behavior. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1999, v:21, n:4, pp:703-746 [Journal]
  143. Xinping Zhu, Wei Qin, Sharad Malik
    Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:707-716 [Journal]
  144. Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin
    Verification Driven Formal Architecture and Microarchitecture Modeling. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:123-132 [Conf]
  145. Xinping Zhu, Sharad Malik
    A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]
  146. Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, K. W. Keutzer
    Statistical timing analysis of combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:126-137 [Journal]
  147. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified timing verification and the transition delay of a logic circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:333-342 [Journal]
  148. Vivek Tiwari, Sharad Malik, Andrew Wolfe
    Power analysis of embedded software: a first step towards software power minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:437-445 [Journal]
  149. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
    Power analysis and minimization techniques for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:123-135 [Journal]
  150. Ying Zhao, Sharad Malik
    Exact memory size estimation for array computations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:517-521 [Journal]

  151. Supporting RTL flow compatibility in a microarchitecture-level design framework. [Citation Graph (, )][DBLP]


  152. Automating Hazard Checking in Transaction-Level Microarchitecture Models. [Citation Graph (, )][DBLP]


  153. A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. [Citation Graph (, )][DBLP]


  154. Runtime validation of memory ordering using constraint graph checking. [Citation Graph (, )][DBLP]


  155. Runtime Validation of Transactional Memory Systems. [Citation Graph (, )][DBLP]


  156. Hardware Verification: Techniques, Methodology and Solutions. [Citation Graph (, )][DBLP]


  157. Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. [Citation Graph (, )][DBLP]


  158. Boolean satisfiability from theoretical hardness to practical success. [Citation Graph (, )][DBLP]


  159. Challenges and Solutions for Late- and Post-Silicon Design. [Citation Graph (, )][DBLP]


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