|
Search the dblp DataBase
Masaaki Yamada:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:641-646 [Conf]
- Xianji Yao, Massaki Yamada, C. L. Liu
A New Approach to the Pin Assignment Problem. [Citation Graph (0, 0)][DBLP] DAC, 1988, pp:566-572 [Conf]
- Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays. [Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:140-143 [Conf]
- M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto
Power and area optimization by reorganizing CMOS complex gate circuits. [Citation Graph (0, 0)][DBLP] ISLPD, 1995, pp:155-160 [Conf]
- Sachio Hayashi, Masaaki Yamada
EMI-noise analysis under ASIC design environment. [Citation Graph (0, 0)][DBLP] ISPD, 1999, pp:16-21 [Conf]
- Sachio Hayashi, Fumihiro Minami, Masaaki Yamada
Full-Chip Analysis Method of ESD Protection Network. [Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:439-444 [Conf]
- Sachio Hayashi, Masaaki Yamada
EMI-noise analysis under ASIC design environment. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1337-1346 [Journal]
- Xianjin Yao, Masaaki Yamada, C. L. Liu
A new approach to the pin assignment problem. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:999-1006 [Journal]
Search in 0.001secs, Finished in 0.002secs
|