A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications. [Citation Graph (, )][DBLP]
A Parallel and Modular Architecture for 802.16e LDPC Codes. [Citation Graph (, )][DBLP]
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]
Architecture-Driven Synthesis of Reconfigurable Cells. [Citation Graph (, )][DBLP]
A New High Performance Multi Gigabit String Matching Engine. [Citation Graph (, )][DBLP]
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. [Citation Graph (, )][DBLP]
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP]
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture. [Citation Graph (, )][DBLP]
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]
Energy efficient sensor node implementations. [Citation Graph (, )][DBLP]
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. [Citation Graph (, )][DBLP]
Constraint-Driven Identification of Application Specific Instructions in the DURASE System. [Citation Graph (, )][DBLP]
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