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Yukiko Kubo:
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- Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:467-472 [Conf]
- Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
Self-reforming routing for stochastic search in VLSI interconnection layout. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:87-92 [Conf]
- Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:220-223 [Conf]
- Yukiko Kubo, Atsushi Takahashi
A global routing method for 2-layer ball grid array packages. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:36-43 [Conf]
- Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
Consistent floorplanning with super hierarchical constraints. [Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:144-149 [Conf]
- Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:467-472 [Conf]
- Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:439-449 [Journal]
- Yukiko Kubo, Atsushi Takahashi
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:725-733 [Journal]
- Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
Consistent floorplanning with hierarchical superconstraints. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:42-49 [Journal]
Chip size estimation based on wiring area. [Citation Graph (, )][DBLP]
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