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Chris H. Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:559-564 [Conf]
  2. Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
    Leakage in nano-scale technologies: mechanisms, impact and design considerations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:6-11 [Conf]
  3. John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
    Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:425-428 [Conf]
  4. Chris H. Kim, Kaushik Roy
    Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:163-167 [Conf]
  5. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling and estimating leakage current in series-parallel CMOS networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:269-274 [Conf]
  6. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    An analytical model for negative bias temperature instability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:493-496 [Conf]
  7. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
    Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:100-105 [Conf]
  8. Jie Gu, Chris H. Kim
    Multi-story power delivery for supply noise reduction and low voltage operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:192-197 [Conf]
  9. Hari Ananthan, Chris H. Kim, Kaushik Roy
    Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:8-13 [Conf]
  10. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device and architecture considerations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:6-9 [Conf]
  11. Chris H. Kim, Kaushik Roy
    Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:251-254 [Conf]
  12. Jonggab Kil, Jie Gu, Chris H. Kim
    A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:67-72 [Conf]
  13. Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim
    Utilizing reverse short channel effect for optimal subthreshold circuit design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:127-130 [Conf]
  14. Jie Gu, John Keane, Chris H. Kim
    Modeling and analysis of leakage induced damping effect in low voltage LSIs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:382-387 [Conf]
  15. Kee-Jong Kim, Chris H. Kim, Kaushik Roy
    TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:59-64 [Conf]
  16. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    Impact of NBTI on SRAM Read Stability and Design for Reliability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:210-218 [Conf]
  17. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Modeling Subthreshold Leakage Current in General Transistor Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:512-513 [Conf]
  18. Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
    Leakage Power Analysis and Reduction for Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:2, pp:68-80 [Journal]
  19. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:349-357 [Journal]
  20. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:646-649 [Journal]
  21. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    NBTI-Aware Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:370-375 [Conf]
  22. Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
    Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:87-92 [Conf]
  23. Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
    Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:474-484 [Conf]
  24. Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim
    Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:821-829 [Journal]
  25. Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy
    Gate leakage reduction for scaled devices using transistor stacking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:716-730 [Journal]

  26. Adaptive techniques for overcoming performance degradation due to aging in digital circuits. [Citation Graph (, )][DBLP]


  27. Circuit techniques for ultra-low power subthreshold SRAMs. [Citation Graph (, )][DBLP]


  28. Sleep transistor sizing and control for resonant supply noise damping. [Citation Graph (, )][DBLP]


  29. An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. [Citation Graph (, )][DBLP]


  30. Enhancing beneficial jitter using phase-shifted clock distribution. [Citation Graph (, )][DBLP]


  31. A multi-story power delivery technique for 3D integrated circuits. [Citation Graph (, )][DBLP]


  32. Variation aware performance analysis of gain cell embedded DRAMs. [Citation Graph (, )][DBLP]


  33. A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. [Citation Graph (, )][DBLP]


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