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Sachin S. Sapatnekar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
    A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. [Citation Graph (1, 0)][DBLP]
    ICPP, 1994, pp:116-125 [Conf]
  2. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:559-564 [Conf]
  3. Haifeng Qian, Sachin S. Sapatnekar
    Hierarchical random-walk algorithms for power grid analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:499-504 [Conf]
  4. Rupesh S. Shelar, Sachin S. Sapatnekar
    An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:87-92 [Conf]
  5. Yong Zhan, Yan Feng, Sachin S. Sapatnekar
    A fixed-die floorplanning algorithm using an analytical approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:771-776 [Conf]
  6. Yong Zhan, Brent Goplen, Sachin S. Sapatnekar
    Electrothermal analysis and optimization techniques for nanoscale integrated circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:219-222 [Conf]
  7. Yong Zhan, Sachin S. Sapatnekar
    Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:87-92 [Conf]
  8. Tianpei Zhang, Sachin S. Sapatnekar
    Buffering global interconnects in structured ASIC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:23-26 [Conf]
  9. Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
    Temperature-aware routing in 3D ICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:309-314 [Conf]
  10. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:189-194 [Conf]
  11. Jiang Hu, Sachin S. Sapatnekar
    FAR-DS: Full-Plane AWE Routing with Driver Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:84-89 [Conf]
  12. Hongliang Chang, Sachin S. Sapatnekar
    Full-chip analysis of leakage power under process variations, including spatial correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:523-528 [Conf]
  13. Rahul B. Deokar, Sachin S. Sapatnekar
    A Fresh Look at Retiming Via Clock Skew Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:310-315 [Conf]
  14. Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
    Net weighting to reduce repeater counts during placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:503-508 [Conf]
  15. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:377-382 [Conf]
  16. John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
    Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:425-428 [Conf]
  17. Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar
    Convex delay models for transistor sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:655-660 [Conf]
  18. Naresh Maheshwari, Sachin S. Sapatnekar
    An Improved Algorithm for Minimum-Area Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:2-7 [Conf]
  19. Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
    Microarchitecture-aware floorplanning using a statistical design of experiments approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:579-584 [Conf]
  20. Vidyasagar Nookala, Sachin S. Sapatnekar
    A method for correcting the functionality of a wire-pipelined circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:570-575 [Conf]
  21. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Random walks in a supply network. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:93-98 [Conf]
  22. Sachin S. Sapatnekar
    RC Interconnect Optimization Under the Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:387-391 [Conf]
  23. Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar
    Robust gate sizing by geometric programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:315-320 [Conf]
  24. Jaskirat Singh, Sachin S. Sapatnekar
    Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:155-160 [Conf]
  25. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    Congestion-driven codesign of power and signal networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:64-69 [Conf]
  26. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Tradeoffs between date oxide leakage and delay for dual Tox circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:761-766 [Conf]
  27. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    MINFLOTRANSIT: min-cost flow based transistor sizing tool. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:649-664 [Conf]
  28. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:150-155 [Conf]
  29. Min Zhao, Sachin S. Sapatnekar
    A New Structural Pattern Matching Algorithm for Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:371-376 [Conf]
  30. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Fast Comparisons of Circuit Implementations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:910-915 [Conf]
  31. Naresh Maheshwari, Sachin S. Sapatnekar
    Efficient Minarea Retiming of Large Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:840-0 [Conf]
  32. Yong Zhan, Sachin S. Sapatnekar
    Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:622-629 [Conf]
  33. Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    A new approach to the use of satisfiability in false path detection. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:308-311 [Conf]
  34. Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    DAG based library-free technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:293-298 [Conf]
  35. Sachin S. Sapatnekar
    Computer-aided design of 3d integrated circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:317- [Conf]
  36. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:706-711 [Conf]
  37. Hongliang Chang, Sachin S. Sapatnekar
    Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:621-626 [Conf]
  38. Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
    A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:220-223 [Conf]
  39. Brent Goplen, Sachin S. Sapatnekar
    Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:86-90 [Conf]
  40. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    A precorrected-FFT method for simulating on-chip inductance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:221-227 [Conf]
  41. Jiang Hu, Sachin S. Sapatnekar
    A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:99-103 [Conf]
  42. Yanbin Jiang, Sachin S. Sapatnekar
    An integrated algorithm for combined placement and libraryless technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:102-106 [Conf]
  43. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Logical effort based technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:419-422 [Conf]
  44. Mahesh Ketkar, Sachin S. Sapatnekar
    Standby power optimization via transistor sizing and dual threshold voltage assignment. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:375-378 [Conf]
  45. Daksh Lehther, Sachin S. Sapatnekar
    Clock tree synthesis for multi-chip modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:50-53 [Conf]
  46. Naresh Maheshwari, Sachin S. Sapatnekar
    Minimum area retiming with equivalent initial states. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:216-219 [Conf]
  47. Haihua Su, Sachin S. Sapatnekar
    Hybrid Structured Clock Network Construction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:333-336 [Conf]
  48. Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
    A chip-level electrostatic discharge simulation strategy. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:315-318 [Conf]
  49. Haifeng Qian, Sachin S. Sapatnekar
    A hybrid linear equation solver and its application in quadratic placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:905-909 [Conf]
  50. Sachin S. Sapatnekar, Weitong Chuang
    Power vs. delay in gate sizing: conflicting objectives? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:463-466 [Conf]
  51. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya
    A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:482-485 [Conf]
  52. Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang
    Convexity-based algorithms for design centering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:206-209 [Conf]
  53. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
    Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:467-470 [Conf]
  54. Rupesh S. Shelar, Sachin S. Sapatnekar
    Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:449-452 [Conf]
  55. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
    Fast Analysis and Optimization of Power/Ground Networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:477-480 [Conf]
  56. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    Marsh: min-area retiming with setup and hold constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:2-6 [Conf]
  57. Yong Zhan, Sachin S. Sapatnekar
    A high efficiency full-chip thermal simulation algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:635-638 [Conf]
  58. Min Zhao, Sachin S. Sapatnekar
    Technology mapping for domino logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:248-251 [Conf]
  59. Min Zhao, Sachin S. Sapatnekar
    Timing-driven partitioning for two-phase domino and mixed static/domino implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:107-110 [Conf]
  60. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    An analytical model for negative bias temperature instability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:493-496 [Conf]
  61. Jiang Hu, Sachin S. Sapatnekar
    Performance Driven Global Routing Through Gradual Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:481-483 [Conf]
  62. Haitian Hu, Sachin S. Sapatnekar
    Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:434-0 [Conf]
  63. Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi
    Efficient Crosstalk Estimation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:266-0 [Conf]
  64. Naresh Maheshwari, Sachin S. Sapatnekar
    A Practical Algorithm for Retiming Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:440-0 [Conf]
  65. Venkatesan Rajappan, Sachin S. Sapatnekar
    An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:76-0 [Conf]
  66. Felipe R. Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    Exact lower bound for the number of switches in series to implement a combinational logic cell. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:357-362 [Conf]
  67. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:228-233 [Conf]
  68. Tianpei Zhang, Sachin S. Sapatnekar
    Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:93-98 [Conf]
  69. Rahul B. Deokar, Sachin S. Sapatnekar
    A Graph-Theoretic Approach to Clock Skew Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:407-410 [Conf]
  70. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    Table look-up based compact modeling for on-chip interconnect timing and noise analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:668-671 [Conf]
  71. Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar
    High Performance CMOS Macromodule Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:179-182 [Conf]
  72. Vidyasagar Nookala, Sachin S. Sapatnekar
    Designing optimized pipelined global interconnects: algorithms and methodology impact. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:608-611 [Conf]
  73. Piyush K. Sancheti, Sachin S. Sapatnekar
    Layout Optimization Using Arbitrarily High Degree Posynomial Models. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:53-56 [Conf]
  74. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Feasible Region Approximation Using Convex Polytopes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1786-1789 [Conf]
  75. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:399-402 [Conf]
  76. Jatuchai Pangjun, Sachin S. Sapatnekar
    Clock distribution using multiple voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:145-150 [Conf]
  77. Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar
    Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:298-303 [Conf]
  78. Guoqiang Chen, Sachin S. Sapatnekar
    Partition-driven standard cell thermal placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:75-80 [Conf]
  79. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  80. Brent Goplen, Sachin S. Sapatnekar
    Thermal via placement in 3D ICs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:167-174 [Conf]
  81. Huibo Hou, Sachin S. Sapatnekar
    Routing tree topology construction to meet interconnect timing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:205-210 [Conf]
  82. Jiang Hu, Sachin S. Sapatnekar
    Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:133-138 [Conf]
  83. Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
    Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:130-135 [Conf]
  84. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
    Datapath routing based on a decongestion metric. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:122-127 [Conf]
  85. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
    A predictive distributed congestion metric and its application to technology mapping. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:210-217 [Conf]
  86. Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
    An efficient technology mapping algorithm targeting routing congestion under delay constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:137-144 [Conf]
  87. Jaskirat Singh, Sachin S. Sapatnekar
    Topology optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:116-123 [Conf]
  88. Jaskirat Singh, Sachin S. Sapatnekar
    A fast algorithm for power grid design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:70-77 [Conf]
  89. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
    An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:68-73 [Conf]
  90. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:132-137 [Conf]
  91. Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
    Tutorial II: Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:5- [Conf]
  92. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    Impact of NBTI on SRAM Read Stability and Design for Reliability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:210-218 [Conf]
  93. Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
    Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:841-846 [Conf]
  94. Rupesh S. Shelar, Sachin S. Sapatnekar
    Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:209-214 [Conf]
  95. Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar
    The Certainty of Uncertainty: Randomness in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:36-47 [Conf]
  96. Leomar S. da Rosa Jr., Felipe S. Marques, Tiago M. G. Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    Fast disjoint transistor networks from BDDs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:137-142 [Conf]
  97. Tianpei Zhang, Sachin S. Sapatnekar
    Optimized pin assignment for lower routing congestion after floorplanning phase. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:17-21 [Conf]
  98. Noel Menezes, Sachin S. Sapatnekar
    Optimization and Analysis Techniques for the Deep Submicron Regime. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:3-4 [Conf]
  99. Sachin S. Sapatnekar
    Capturing the Effect of Crosstalk on Delay. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:364-369 [Conf]
  100. Sachin S. Sapatnekar
    High-Performance Power Grids For Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:839-844 [Conf]
  101. Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani
    High-Speed Interconnect Technology: On-Chip and Off-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:7-0 [Conf]
  102. Jatan C. Shah, Sachin S. Sapatnekar
    Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:346-351 [Conf]
  103. Rupesh S. Shelar, Sachin S. Sapatnekar
    An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:87-92 [Conf]
  104. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
    Placement and Routing in 3D Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:520-531 [Journal]
  105. Sachin S. Sapatnekar
    An EDA compendium. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:74-75 [Journal]
  106. Sachin S. Sapatnekar
    Empowering the designer. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:280-281 [Journal]
  107. Sachin S. Sapatnekar
    Designing "Vary" Good Circuitry. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:596-597 [Journal]
  108. Sachin S. Sapatnekar
    Book Reviews: Plumbing the Depths of Leakage. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:318-319 [Journal]
  109. Sachin S. Sapatnekar, Grant Martin
    DAC Highlights. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:182-184 [Journal]
  110. Sachin S. Sapatnekar, Kevin J. Nowka
    Guest Editors' Introduction: New Dimensions in 3D Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:496-497 [Journal]
  111. Sachin S. Sapatnekar, Haihua Su
    Analysis and Optimization of Power Grids. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:7-15 [Journal]
  112. Jiang Hu, Sachin S. Sapatnekar
    A survey on multi-net global routing for integrated circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:1-49 [Journal]
  113. Naresh Maheshwari, Sachin S. Sapatnekar
    Retiming control logic. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:28, n:1, pp:33-53 [Journal]
  114. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
    Probability-driven routing in a datapath environment. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:159-182 [Journal]
  115. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1140-1145 [Journal]
  116. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A practical methodology for early buffer and wire resource allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:573-583 [Journal]
  117. Charles J. Alpert, Sachin S. Sapatnekar
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:385-386 [Journal]
  118. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal]
  119. Jiang Hu, Sachin S. Sapatnekar
    Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:446-458 [Journal]
  120. Hongliang Chang, Sachin S. Sapatnekar
    Statistical timing analysis under spatial correlations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1467-1482 [Journal]
  121. Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
    Timing and area optimization for standard-cell VLSI circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:308-320 [Journal]
  122. Jiang Hu, Sachin S. Sapatnekar
    A timing-constrained simultaneous global routing algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1025-1036 [Journal]
  123. Brent Goplen, Sachin S. Sapatnekar
    Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:692-709 [Journal]
  124. Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
    Non-Hanan routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:436-444 [Journal]
  125. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
  126. Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar
    A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:779-788 [Journal]
  127. Martin Kuhlmann, Sachin S. Sapatnekar
    Exact and efficient crosstalk estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:858-866 [Journal]
  128. Naresh Maheshwari, Sachin S. Sapatnekar
    Optimizing large multiphase level-clocked circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1249-1264 [Journal]
  129. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:676-682 [Journal]
  130. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Power grid analysis using random walks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1204-1224 [Journal]
  131. Piyush K. Sancheti, Sachin S. Sapatnekar
    Optimal design of macrocells for low power and high speed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1160-1166 [Journal]
  132. Sachin S. Sapatnekar
    A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:550-559 [Journal]
  133. Sachin S. Sapatnekar
    Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1001-1011 [Journal]
  134. Sachin S. Sapatnekar, Rahul B. Deokar
    Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1237-1248 [Journal]
  135. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
    An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1621-1634 [Journal]
  136. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Convexity-based algorithms for design centering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1536-1549 [Journal]
  137. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
    Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:173-182 [Journal]
  138. Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
    Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:625-636 [Journal]
  139. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
    A predictive distributed congestion metric with application to technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:696-710 [Journal]
  140. Jaskirat Singh, Sachin S. Sapatnekar
    Congestion-aware topology optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:683-695 [Journal]
  141. Jaskirat Singh, Sachin S. Sapatnekar
    Partition-Based Algorithm for Power Grid Design Using Locality. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:664-677 [Journal]
  142. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
    Analysis and optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1533-1544 [Journal]
  143. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    A methodology for the simultaneous design of supply and signal networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1614-1624 [Journal]
  144. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
    Optimal decoupling capacitor sizing and placement for standard-cell layout designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:428-436 [Journal]
  145. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    Fast and exact transistor sizing based on iterative relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:568-581 [Journal]
  146. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:159-168 [Journal]
  147. Min Zhao, Sachin S. Sapatnekar
    Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1322-1336 [Journal]
  148. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:273-289 [Journal]
  149. Sachin S. Sapatnekar, Weitong Chuang
    Power-delay optimizations in gate sizing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:98-114 [Journal]
  150. Min Zhao, Sachin S. Sapatnekar
    Technology mapping algorithms for domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:306-335 [Journal]
  151. Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
    A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:11, pp:1098-1116 [Journal]
  152. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Fast comparisons of circuit implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1329-1339 [Journal]
  153. Rupesh S. Shelar, Sachin S. Sapatnekar
    BDD decomposition for delay oriented pass transistor logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:957-970 [Journal]
  154. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1362-1375 [Journal]
  155. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
    NBTI-Aware Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:370-375 [Conf]
  156. Brent Goplen, Sachin S. Sapatnekar
    Placement of 3D ICs with Thermal and Interlayer Via Considerations. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:626-631 [Conf]
  157. Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
    Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:87-92 [Conf]
  158. Qunzeng Liu, Sachin S. Sapatnekar
    Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:497-502 [Conf]
  159. Hongliang Chang, Sachin S. Sapatnekar
    Prediction of leakage power under process uncertainties. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  160. Tianpei Zhang, Sachin S. Sapatnekar
    Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:624-636 [Journal]
  161. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
    Interleaving buffer insertion and transistor sizing into a single optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:625-633 [Journal]
  162. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
    Technology mapping for high-performance static CMOS and pass transistor logic designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:577-589 [Journal]
  163. Jatuchai Pangjun, Sachin S. Sapatnekar
    Low-power clock distribution using multiple voltages and reduced swings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:309-318 [Journal]
  164. Haitian Hu, Sachin S. Sapatnekar
    Efficient inductance extraction using circuit-aware techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:746-761 [Journal]
  165. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1094-1105 [Journal]

  166. Addressing thermal and power delivery bottlenecks in 3D circuits. [Citation Graph (, )][DBLP]


  167. Adaptive techniques for overcoming performance degradation due to aging in digital circuits. [Citation Graph (, )][DBLP]


  168. Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. [Citation Graph (, )][DBLP]


  169. Reinventing EDA with manycore processors. [Citation Graph (, )][DBLP]


  170. A progressive-ILP based routing algorithm for cross-referencing biochips. [Citation Graph (, )][DBLP]


  171. A framework for block-based timing sensitivity analysis. [Citation Graph (, )][DBLP]


  172. Module assignment for pin-limited designs under the stacked-Vdd paradigm. [Citation Graph (, )][DBLP]


  173. Clustering based pruning for statistical criticality computation under process variations. [Citation Graph (, )][DBLP]


  174. A general model for performance optimization of sequential systems. [Citation Graph (, )][DBLP]


  175. Fast estimation of area-delay trade-offs in circuit sizing. [Citation Graph (, )][DBLP]


  176. Comparing simulation techniques for microarchitecture-aware floorplanning. [Citation Graph (, )][DBLP]


  177. Synthesizing a representative critical path for post-silicon delay prediction. [Citation Graph (, )][DBLP]


  178. Adding a new dimension to physical design. [Citation Graph (, )][DBLP]


  179. Dummy fill optimization for enhanced manufacturability. [Citation Graph (, )][DBLP]


  180. Scalable methods for the analysis and optimization of gate oxide breakdown. [Citation Graph (, )][DBLP]


  181. Technical perspective - Where the chips may fall. [Citation Graph (, )][DBLP]


  182. Book Review: An Assay of Biochips. [Citation Graph (, )][DBLP]


  183. DAC Highlights. [Citation Graph (, )][DBLP]


  184. Building your yield of dreams. [Citation Graph (, )][DBLP]


  185. Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. [Citation Graph (, )][DBLP]


  186. Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. [Citation Graph (, )][DBLP]


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