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Hiroo Masuda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda
    DEPOGIT: dense power-ground interconnect architecture for physical design integrity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:517-522 [Conf]
  2. Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori
    TCAD/DA for MPU and ASIC Development. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:129-134 [Conf]
  3. Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda
    Large-scale linear circuit simulation with an inversed inductance matrix. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:511-516 [Conf]
  4. Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
    Approach for physical design in sub-100 nm era. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5934-5937 [Conf]
  5. Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
    Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:586-591 [Conf]
  6. Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
    Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:153-158 [Conf]
  7. Takashi Sato, Hiroo Masuda
    Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:395-400 [Conf]
  8. Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato
    A New Design-Centering Methodology for VLSI Device Development. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:452-461 [Journal]
  9. Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro
    MOSTSM: a physically based charge conservative MOSFET model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1229-1236 [Journal]
  10. Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki
    A submicrometer MOS transistor I-V model for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:161-170 [Journal]

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