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Young-Su Kwon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung
    Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:806-811 [Conf]
  2. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:559-564 [Conf]
  3. Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    A New Single-Clock Flip-Clop for Half-Swing Clocking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:117-120 [Conf]
  4. Jae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:499-502 [Conf]
  5. Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung
    Fast development of source-level debugging system using hardware emulation (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:401-404 [Conf]
  6. Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung
    Communication-efficient hardware acceleration for fast functional simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:293-298 [Conf]
  7. Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
    Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:45-48 [Conf]
  8. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: An Application Specific DSP Development System. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:800-803 [Conf]
  9. Young-Su Kwon, Chong-Min Kyung
    Functional Coverage Metric Generation from Temporal Event Relation Graph. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:670-671 [Conf]
  10. Young-Su Kwon, Bong-Il Park, Chong-Min Kyung
    SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:419-425 [Conf]
  11. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  12. Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel
    A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:65-72 [Conf]
  13. Young-Su Kwon, Woo-Seung Yang, Chong-Min Kyung
    Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:123-128 [Conf]
  14. Young-Su Kwon, Chong-Min Kyung
    Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1444-1456 [Journal]
  15. Young-Su Kwon, Chong-Min Kyung
    Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:341-350 [Journal]
  16. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: an application-specific programmable DSP development system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:173-183 [Journal]

  17. Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor. [Citation Graph (, )][DBLP]

  18. Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. [Citation Graph (, )][DBLP]

  19. Implmentation of digital audio effect SoC. [Citation Graph (, )][DBLP]

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