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Kanupriya Gulati: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
    Controlling inductive cross-talk and power in off-chip buses using CODECs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:850-855 [Conf]
  2. Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
    A design flow to optimize circuit delay by using standard cells and PLAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf]
  3. Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
    Network coding for routability improvement in VLSI. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:820-823 [Conf]
  4. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:111-114 [Conf]
  5. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    A Structured ASIC Design Approach Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1787-1790 [Conf]
  6. Chunjie Duan, K. Gulat, Sunil P. Khatri
    Memory-based crosstalk canceling CODECs for on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  7. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    A probabilistic method to determine the minimum leakage vector for combinational designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  8. Kanupriya Gulati, M. Lovell, Sunil P. Khatri
    Efficient don't care computation for hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  9. Fast circuit simulation on graphics processing units. [Citation Graph (, )][DBLP]

  10. Accelerating statistical static timing analysis using graphics processing units. [Citation Graph (, )][DBLP]

  11. Towards acceleration of fault simulation using graphics processing units. [Citation Graph (, )][DBLP]

  12. Toggle Equivalence Preserving (TEP) Logic Optimization. [Citation Graph (, )][DBLP]

  13. On Complexity of Internal and External Equivalence Checking. [Citation Graph (, )][DBLP]

  14. Closed-loop modeling of power and temperature profiles of FPGAs. [Citation Graph (, )][DBLP]

  15. Improving FPGA routability using network coding. [Citation Graph (, )][DBLP]

  16. Low power and high performance sram design using bank-based selective forward body bias. [Citation Graph (, )][DBLP]

  17. Robust window-based multi-node technology-independent logic minimization. [Citation Graph (, )][DBLP]

  18. Boolean satisfiability on a graphics processor. [Citation Graph (, )][DBLP]

  19. An Efficient, Scalable Hardware Engine for Boolean SATisfiability. [Citation Graph (, )][DBLP]

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