The SCEAS System
| |||||||

## Search the dblp DataBase
Kanupriya Gulati:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
**Controlling inductive cross-talk and power in off-chip buses using CODECs.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:850-855 [Conf] - Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
**A design flow to optimize circuit delay by using standard cells and PLAs.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf] - Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
**Network coding for routability improvement in VLSI.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:820-823 [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:111-114 [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**A Structured ASIC Design Approach Using Pass Transistor Logic.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1787-1790 [Conf] - Chunjie Duan, K. Gulat, Sunil P. Khatri
**Memory-based crosstalk canceling CODECs for on-chip buses.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**A probabilistic method to determine the minimum leakage vector for combinational designs.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Kanupriya Gulati, M. Lovell, Sunil P. Khatri
**Efficient don't care computation for hierarchical designs.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] **Fast circuit simulation on graphics processing units.**[Citation Graph (, )][DBLP]**Accelerating statistical static timing analysis using graphics processing units.**[Citation Graph (, )][DBLP]**Towards acceleration of fault simulation using graphics processing units.**[Citation Graph (, )][DBLP]**Toggle Equivalence Preserving (TEP) Logic Optimization.**[Citation Graph (, )][DBLP]**On Complexity of Internal and External Equivalence Checking.**[Citation Graph (, )][DBLP]**Closed-loop modeling of power and temperature profiles of FPGAs.**[Citation Graph (, )][DBLP]**Improving FPGA routability using network coding.**[Citation Graph (, )][DBLP]**Low power and high performance sram design using bank-based selective forward body bias.**[Citation Graph (, )][DBLP]**Robust window-based multi-node technology-independent logic minimization.**[Citation Graph (, )][DBLP]**Boolean satisfiability on a graphics processor.**[Citation Graph (, )][DBLP]**An Efficient, Scalable Hardware Engine for Boolean SATisfiability.**[Citation Graph (, )][DBLP]
Search in 0.004secs, Finished in 0.005secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |